Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor

An apparatus for reducing replays, the apparatus comprising:

• a multi-core processor, comprising a plurality of cores, wherein each of said plurality of cores comprises:
• a first reservation station, configured to dispatch a first load micro instruction, and configured to detect and indicate on a hold bus if said first load micro instruction is a specified load micro instruction directed to retrieve an operand from one of a plurality of prescribed resources other than on-core cache memory, wherein said specified load instruction comprises a load instruction resulting from execution of an x86 special bus cycle;
• a second reservation station, coupled to said hold bus, configured to dispatch one or more younger micro instructions therein that depend on said first load micro instruction for execution after said first number of clock cycles following dispatch of said first load micro instruction, and if it is indicated on said hold bus that said first load micro instruction is said specified load micro instruction, said second reservation station is configured to stall dispatch of said one or more younger micro instructions until said first load micro instruction has retrieved said operand;
• and
• load execution logic, coupled to said first reservation station, configured to receive and execute said first load micro instruction.

A method for reducing replays in an out-of-order processor, the method comprising:

• via a first reservation station, dispatching a first load micro instruction, and detecting and indicating on a hold bus if the first load micro instruction is a specified load micro instruction directed to retrieve an operand from the one of a plurality of prescribed resources other than on-core cache memory, wherein the specified load instruction comprises a load instruction resulting from execution of an x86 special bus cycle;
• and
• via a second reservation station that is coupled to the hold bus, dispatching one or more younger micro instructions therein that depend on the first load micro instruction for execution after the first number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the first load micro instruction is the specified load micro instruction, stalling dispatch of the one or more younger micro instructions until the first load micro instruction has retrieved the operand;
• and
• via load execution logic that is coupled to the first reservation station, receiving and executing the first load micro instruction.