Method and apparatus for linear function processing in pipelined storage circuits
AssigneeAltera Corporation
InventorPohrong Rita Chu
Life of this patent
Estimating the term…
Abstract
An integrated circuit may have processing and storage circuits that perform read-modify-write operations on a wide data path. A CAD tool may partition the wide data path into data path subsets based on the width of the wide data path, the characteristics of the processing and storage circuits, and various constraints such as resource constraints and timing constraints. The CAD tool may also instantiate corresponding pipelined circuitry. The pipelined circuitry may be arranged in slices with cascaded processing and storage circuits. Each processing and storage circuit in a slice may perform a read-modify-write operation based on the corresponding data path subset and any prior result produced by other processing and storage circuits.
Claims20
A method for operating an integrated circuit, comprising:
- receiving data from a data path;
- partitioning the data into multiple data sets, wherein the multiple data sets include first and second data sets;
- receiving the first data set of the multiple data sets at a first input port;
- retrieving a third data set from a first storage circuit;
- using a first processing circuit to perform a pipelined read-modify-write operation based on the first and third data sets, wherein using the first processing circuit to perform the pipelined read-modify-write operation based on the first and third data sets comprises generating an output data set based on the first and third data sets;
- receiving the second data set of the multiple data sets at a second input port;
- retrieving a fourth data set from a second storage circuit;
- and
- using a second processing circuit to perform a pipelined read-modify-write operation based on the output data set from the first processing circuit, the second data set, and the fourth data set.
A method for operating a computer aided design tool to implement a circuit design in a programmable integrated circuit, comprising:
- determining a first number that is smaller than or equal to the maximum width of a configurable storage circuit in the circuit design, wherein the first number divides a given number of bits into a first quantity of subsets;
- partitioning the given number of bits into the first quantity of subsets, wherein a first subset of the first quantity of subsets includes a first number of bits;
- generating an estimated delay for performing a pipelined read-modify-write operation on the configurable storage circuit using the first number of bits;
- determining whether the estimated delay is greater than a desired maximum delay constraint;
- and
- generating a mask-level layout description of the programmable integrated circuit after determining whether the estimated delay is greater than the desired maximum delay constraint.
An integrated circuit comprising:
- an output;
- a plurality of inputs that receives input data;
- first processing and storage circuitry that includes a first processing circuit and a first storage circuit, wherein the first processing circuit receives a first subset of the input data from a first input in the plurality of inputs and receives first stored data from the first storage circuit, and wherein the first processing circuit generates first output data based on the first subset of input data and the first stored data, writes the first output data into the first storage circuit, and sends the first output data to the output;
- and
- second processing and storage circuitry that includes a second processing circuit and a second storage circuit, wherein the second processing circuit receives a second subset of input data from a second input of the plurality of inputs, second stored data from the second storage circuit and the output data from the first processing circuit, and wherein the second processing circuit generates second output data based on the second subset of input data, the second stored data, and the output data.
Dependencies are inferred from the claim text.