Instruction for determining histograms
AssigneeIntel Corporation
InventorShih Shigjong Kuo
Life of this patent
Estimating the term…
Abstract
A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.
Claims22
A processor comprising:
- a functional unit of an instruction execution pipeline to execute an instruction to cause:
- comparison bank circuitry to compare one or more elements of a first input vector against an element of a second input vector;
- and
- adder circuitry coupled to said comparison bank circuitry to add a number of elements of said second input vector that match a value of said first input vector on an element by element basis of said first input vector, wherein said functional unit comprises wiring to fan-out said element of said second input vector to multiple comparison circuits of said comparison bank circuitry to perform multiple comparisons of said element against said one or more elements of said first input vector, and wiring to fan-in multiple respective values from said multiple comparison circuits to said adder circuitry to produce a scalar summation value for said element of said second input vector against said one or more elements of said first input vector.
A method comprising:
- determining a histogram through execution of a first instruction, said executing of said first instruction comprising:
- comparing elements of a first input vector against an element of a second input vector with comparison bank circuitry of a processor;
- and
- adding a number of elements of said second input vector that match a value of said first input vector on an element by element basis of said first input vector with adder circuitry of a processor, wherein the processor comprises wiring to fan-out said element of said second input vector to multiple comparison circuits of said comparison bank circuitry to perform multiple comparisons of said element against said elements of said first input vector, and wiring to fan-in multiple respective values from said multiple comparison circuits to said adder circuitry to produce a scalar summation value for said element of said second input vector against said elements of said first input vector.
A non-transitory machine readable medium containing program code that when processed by a processor causes the processor to perform a method comprising:
- determining a histogram through execution of a first instruction, said executing of said first instruction including:
- comparing elements of a first input vector against an element of a second input vector with comparison bank circuitry of a processor;
- and
- adding a number of elements of said second input vector that match a value of said first input vector on an element by element basis of said first input vector with adder circuitry of a processor, wherein the processor comprises wiring to fan-out said element of said second input vector to multiple comparison circuits of said comparison bank circuitry to perform multiple comparisons of said element against said elements of said first input vector, and wiring to fan-in multiple respective values from said multiple comparison circuits to said adder circuitry to produce a scalar summation value for said element of said second input vector against said elements of said first input vector.
Dependencies are inferred from the claim text.