Data storage device, method thereof, and data processing system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsTae Min Jeong, Hyun Wook Lee, Jae Chun Park, Soon Jae Won
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Abstract
A data storage device includes a central processing unit (CPU); a peripheral device; a power management unit (PMU) configured to control a power supply to the CPU and the peripheral device; and a receiver configured to transmit a second signal to the PMU through a second transmission path after transmitting a first signal to the CPU through a first transmission path, the receiver being configured such that the first and second signals transmitted by the receiver are signals that were output from a host.
Claims15
A data storage device comprising:
- a central processing unit (CPU);
- a peripheral device;
- a power management unit (PMU) configured to control a power supply to the CPU and the peripheral device;
- and
- a receiver configured to transmit a second signal to the PMU through a second transmission path after transmitting a first signal to the CPU through a first transmission path,
- the receiver being configured such that the first and second signals transmitted by the receiver are signals that were output from a host,
- the first signal being a sleep signal, which the CPU is configured to respond to by causing the data storage device to transition from a power-on state to a lower power state,
- wherein,
- the CPU is configured to generate a control signal based on the first signal and transmit the control signal to the PMU, and
- the PMU is configured to intercept power supplied to the CPU and the peripheral device in response to the control signal.
A data processing system comprising:
- a host;
- a data storage device;
- a first interface connected between the host and the data storage device;
- and
- a second interface connected between the host and the data storage device,
- wherein the data storage device is configured to enter an idle state, and the data storage device is configured to control the second interface such that a state of the second interface is a power-off state based on a first data packet, the first data packet being a data packet which is output from the host and input through the first interface, and
- the data storage device is configured such that the data storage device transitions from the idle state to an active state, and the data storage device is configured to control the second interface such the state of the second interface is a power-on state based on a second data packet, the second data packet being a data packet which is output from the host and input through the first interface.
A data processing system comprising:
- a host;
- a data storage device;
- a first interface connected between the host and the data storage device;
- and
- a second interface connected between the host and the data storage device,
- the data storage device being configured to receive a first signal from the host through the first interface,
- the data storage device being configured such that, based on receiving the first signal, the data storage device controls the second interface to transition from a power-on state to a lower power state, the lower power state being a state in which the second interface uses less power than the second interface uses when in the power-on state,
- the data storage device being configured to receive a second signal from the host through the first interface,
- the data storage device being configured such that, based on receiving the second signal, the data storage device controls the second interface to transition from the lower power state to the power-on state.
Dependencies are inferred from the claim text.