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US 9,804,656 B2Granted
Micro-architectural energy monitor event-assisted temperature sensing
AssigneeIntel Corporation
InventorsLinda L. Hurd, Eric C. Samson
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Abstract
Methods and apparatus relating to micro-architectural energy monitor event-assisted temperature sensing are described. In one embodiment, at least one of a plurality of slices of a computational logic or at least one of a plurality of sub-slices of the computational logic are powered down or powered up based on a comparison of a temperature value, that is determined based on one or more micro-architectural events, and a threshold value. Other embodiments are also disclosed and claimed.
Claims33
A processor comprising:
- computational logic having a plurality of slices and at least one unslice, wherein each of the plurality of slices is to comprise a plurality of sub-slices to perform one or more computations;
- and
- logic to cause at least one of the plurality of slices or at least one of the plurality of sub-slices to power down or power up based on a comparison of a temperature value, to be determined based on one or more micro-architectural events that are to indicate an active status and a level of activity within one or more components of the processor, and a threshold value, wherein the temperature value is to be determined based on a first temperature value, corresponding to the at least one of the plurality of slices or the at least one of the plurality of sub-slices, and a second temperature value for a neighboring slice or sub-slice, wherein the second temperature value is to correspond to an inactive temperature value of the neighboring slice or sub-slice, wherein the logic is to cause at least one of the plurality of slices or at least one of the plurality of sub-slices to power down or power up based at least in part on a ratio of leakage to dynamic power.
A method comprising:
- causing at least one of a plurality of slices of a computational logic or at least one of a plurality of sub-slices of the computational logic to power down or power up based on a comparison of a temperature value, to be determined based on one or more micro-architectural events that are to indicate an active status and a level of activity within one or more components to be coupled to the computational logic, and a threshold value,
- wherein the computational logic comprises at least one unslice, the plurality of slices and wherein each of the plurality of slices comprises a plurality of sub-slices to perform one or more computations, wherein the temperature value is determined based on a first temperature value, corresponding to the at least one of the plurality of slices or the at least one of the plurality of sub-slices, and a second temperature value for a neighboring slice or sub-slice, wherein the second temperature value corresponds to an inactive temperature value of the neighboring slice or sub-slice, wherein at least one of the plurality of slices or at least one of the plurality of sub-slices is powered down or powered up based at least in part on a ratio of leakage to dynamic power.
A system comprising:
- a processor having one or more processor cores;
- memory to store data to be accessed by at least one of the one or more processor cores;
- the processor comprising:
- computational logic having a plurality of slices and at least one unslice, wherein each of the plurality of slices is to comprise a plurality of sub-slices to perform one or more computations;
- and
- logic to cause at least one of the plurality of slices or at least one of the plurality of sub-slices to power down or power up based on a comparison of a temperature value, to be determined based on one or more micro-architectural events, and a threshold value, wherein the temperature value is to be determined based on a first temperature value, corresponding to the at least one of the plurality of slices or the at least one of the plurality of sub-slices, and a second temperature value for a neighboring slice or sub-slice, wherein the second temperature value is to correspond to an inactive temperature value of the neighboring slice or sub-slice, wherein the logic is to cause at least one of the plurality of slices or at least one of the plurality of sub-slices to power down or power up based at least in part on a ratio of leakage to dynamic power.
3 more elements
A non-transitory computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:
- cause at least one of a plurality of slices of a computational logic or at least one of a plurality of sub-slices of the computational logic to power down or power up based on a comparison of a temperature value, to be determined based on one or more micro-architectural events, and a threshold value,
- wherein the computational logic comprises at least one unslice, the plurality of slices and wherein each of the plurality of slices comprises a plurality of sub-slices to perform one or more computations wherein the temperature value is determined based on a first temperature value, corresponding to the at least one of the plurality of slices or the at least one of the plurality of sub-slices, and a second temperature value for a neighboring slice or sub-slice, wherein the second temperature value is to correspond to an inactive temperature value of the neighboring slice or sub-slice, wherein at least one of the plurality of slices or at least one of the plurality of sub-slices is caused to power down or power up based at least in part on a ratio of leakage to dynamic power.
Dependencies are inferred from the claim text.