Method and device for generating an adjustable bandgap reference voltage

A circuit comprising:

• a first transistor comprising
• a first source coupled to a first input node,
• a first gate, and
• a first drain;
• a second transistor comprising
• a second source coupled to a second input node,
• a second gate, and
• a second drain coupled to the second gate;
• a first resistor coupled between the first source and a second supply node;
• a first BJT coupled between the first resistor and the second supply node;
• a second BJT coupled between the second source and the second supply node;
• a third transistor comprising
• a third gate,
• a third source coupled to a first supply node, and
• a third drain coupled to the first input node;
• and
• a fourth transistor comprising
• a fourth gate coupled to the third gate;
• a fourth source coupled to the first supply node;
• a fourth drain coupled to the second input node;
• a fifth transistor coupled between the first transistor and the second supply node, the fifth transistor comprising a fifth gate;
• and
• a sixth transistor coupled between the second transistor and the second supply node, the sixth transistor comprising a sixth gate coupled to the fifth gate;
• a seventh transistor comprising
• a seventh gate coupled to the second gate,
• a seventh source, and
• a seventh drain;
• a second resistor coupled between the seventh source and the second supply node;
• an eighth transistor comprising
• an eighth source coupled to the first input node,
• an eighth gate coupled to the second gate, and
• an eighth drain;
• and
• a ninth transistor comprising
• a ninth source coupled to the second supply node,
• a ninth gate, and
• a ninth drain coupled to the eighth drain.

A circuit comprising:

• a first PMOS transistor comprising
• a first PMOS load path coupled to a first input node, and
• a first PMOS gate;
• a second PMOS transistor comprising
• a second PMOS load path coupled to a second input node, and
• a second PMOS gate coupled to the second PMOS load path;
• a first resistor coupled between the first PMOS load path and a ground node;
• a first diode coupled between the first resistor and the ground node;
• a second diode coupled between the second PMOS load path and the ground node;
• a third PMOS transistor comprising
• a third PMOS load path coupled to the first PMOS load path,
• the third PMOS load path coupled between a supply node and the first input node;
• a fourth PMOS transistor comprising
• a fourth PMOS gate coupled to a third PMOS gate,
• a fourth PMOS load path coupled between the supply node and the second
• input node;
• a first NMOS transistor comprising a first NMOS load path coupled between the first PMOS load path and the ground node;
• a second NMOS transistor comprising a second NMOS load path coupled between the second PMOS load path and the ground node;
• a fifth PMOS transistor comprising
• a fifth PMOS gate coupled to the second PMOS gate, and
• a fifth PMOS load path;
• a second resistor coupled between the fifth PMOS load path and the ground node;
• a sixth PMOS transistor comprising
• a sixth PMOS gate,
• a sixth PMOS load path coupled between the supply node and the second resistor;
• a third NMOS transistor comprising a third NMOS load path coupled between the fifth PMOS load path and the ground node;
• a fifteenth PMOS transistor comprising
• a fifteenth PMOS load path coupled between the sixth PMOS load path and the ground node, and
• a fifteenth PMOS gate;
• a ninth NMOS transistor comprising a ninth NMOS load path coupled between the fifteenth PMOS load path and the ground node;
• and
• a sixteenth PMOS transistor comprising
• a sixteenth PMOS gate coupled to the fifteenth PMOS gate, and
• a sixteenth PMOS load path coupled between the second input node and the ground node.