Pixel electrode, array substrate and display panel

An array substrate, comprising:

• a first substrate and a pixel electrode layer located on a surface of the first substrate, wherein the pixel electrode layer comprises:
• a plurality of sub-pixel regions, wherein each of the plurality of sub-pixel regions comprises at least one pixel electrode;
• a plurality of thin film transistors, wherein each of the plurality of thin film transistors comprises a gate electrode, a source electrode and a drain electrode, the drain electrode being connected to the pixel electrode;
• a plurality of scanning lines, which are respectively connected to the gate electrodes of the thin film transistors and are configured to control the thin film transistors to be on or off;
• and
• a plurality of data lines, which are respectively connected to the source electrodes of the thin film transistors and are configured to provide the pixel electrodes with a driving signal via the thin film transistors;
• wherein the pixel electrode comprises:
• a main pixel electrode comprising one main electrode extending in a first direction;
• and
• a plurality of extension portions connected with the main electrode, wherein the plurality of extension portions comprises:
• a first end portion and a second end portion respectively located at two ends of the main electrode and extending along a same direction, wherein the said same direction is not parallel to the first direction;
• and
• a first extending portion connected to the first end portion and extending in a second direction, wherein the second direction intersects with the first direction, and a width of the first extending portion of the pixel electrode is less than a width of the main electrode in the main pixel electrode.

A display panel, comprising:

• an array substrate;
• a color film substrate arranged opposite to the array substrate;
• and
• a liquid crystal layer located between the array substrate and the color film substrate;
• wherein the array substrate comprises a first substrate and a pixel electrode layer located on a surface of the first substrate, and wherein the pixel electrode layer comprises:
• a plurality of sub-pixel regions, wherein each of the plurality of sub-pixel regions comprises at least one pixel electrode;
• a plurality of thin film transistors, wherein each of the plurality of thin film transistors comprises a gate electrode, a source electrode and a drain electrode, wherein the drain electrode being connected to the pixel electrode;
• a plurality of scanning lines, which are respectively connected to the gate electrodes of the thin film transistors and are configured to control the thin film transistors to be on or off;
• and
• a plurality of data lines, which are respectively connected to the source electrodes of the thin film transistors and are configured to provide the pixel electrodes with a driving signal via the thin film transistors;
• wherein the pixel electrode comprises:
• a main pixel electrode comprising one main electrode extending in a first direction;
• and
• a plurality of extension portions connected with the main electrode, wherein the plurality of extension portions comprises:
• a first end portion and a second end portion respectively located at two ends of the main electrode and extending along a same direction, wherein the said same direction is not parallel to the first direction;
• and
• a first extending portion connected to the first end portion and extending in a second direction, wherein the second direction intersects with the first direction, and a width of the first extending portion of the pixel electrode is less than a width of the main electrode in the main pixel electrode.