Configurable vertical integration
OwnerGlenn J Leedyinventor
Life of this patent
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Abstract
The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.
Claims19
A method of information processing using a stacked integrated circuit comprising a network comprising a plurality of control circuit portions, including redundant control circuit portions, a plurality of information bus circuit portions, and a plurality of processing circuit portions, wherein for purposes of redundancy there are a plurality of separate or partially separate interconnection paths interconnecting at least two control circuit portions of the plurality of control circuit portions, the method comprising:
- establishing a control network using at least one of the plurality of separate or partially separate interconnection paths the control network configuring or enabling or disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;
- and performing information processing between at least two of the processing circuit portions.
A method of integrated circuit testing of a stacked integrated circuit comprising a plurality of control circuit portions, including redundant control circuit portions, wherein there are a plurality of separate or partially separate, redundant interconnection paths interconnecting at least two control circuit portions of the plurality of control circuit portions, and a plurality of circuit portions comprising at least one of a bus circuit portion and a processing circuit portion, the method comprising:
- i. establishing a control network using at least one of the plurality of separate or partially separate, redundant interconnection paths;
- ii. disabling the plurality of circuit portions;
- iii selecting for testing at one time at least one of the plurality of circuit portions, iv. using the control network to enable for testing the selected at least one of the plurality of circuit portions, v. testing the selected at least one of the plurality of circuit portions;
- vi. using the control network to disable the selected at least one of the plurality of circuit portions if it failed testing, and vii. repeating steps ii. through vi. until a majority or all of the plurality of circuit portions have been tested.
Dependencies are inferred from the claim text.