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US 9,799,391 B1Granted
Dram circuit, redundant refresh circuit and refresh method
AssigneeNanya Technology Corporation
InventorTzu Yin Wei
Life of this patent
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Abstract
A DRAM circuit includes an array having a normal word line, a first redundant word line and a second redundant word line immediately adjacent to the first redundant word line. The second redundant word line is activated if the normal word line is assigned, by a memory controller external to the DRAM circuit, to be activated. A redundant refresh circuit is configured to determine that the first redundant word line is required to be refreshed in response to the second redundant word line being activated; and a row decoder is configured to, according to the determination of the redundant refresh circuit, refresh the first redundant word line.
Claims19
A DRAM circuit, comprising:
- an array including a normal word line, a first redundant word line and a second redundant word line immediately adjacent to the first redundant word line, wherein the second redundant word line is activated if the normal word line is assigned, by a memory controller external to the DRAM circuit, to be activated, wherein the normal word line is a second normal word line, the array further includes a first normal word line immediately adjacent to the second normal word line;
- a redundant refresh circuit configured to determine that the first redundant word line is required to be refreshed in response to the second redundant word line being activated;
- a row decoder configured to, according to the determination of the redundant refresh circuit, refresh the first redundant word line;
- and
- a target row counter configured to deter mine that the first normal word line is required to be refreshed in response to the second normal word line being assigned to be activated, wherein the row decoder ignores the determination from the target row counter, and, according to the determination from the redundant refresh circuit, refresh the first redundant word line.
2 more elements
A redundant refresh circuit in a DRAM circuit, comprising:
- a latch configured to receive a determination indicating that a second redundant word line of an array is to be activated, and retain the determination, wherein the second redundant word line is activated if a word line of the array is assigned to be activated, by a command external to the redundant refresh circuit;
- and
- a shift circuit configured to determine that a first redundant word line of the array is required to be refreshed according to the determination from the latch, wherein the first redundant word line is immediately adjacent to the second redundant word line.
A refresh method of a redundant refresh circuit in a DRAM circuit, comprising:
- activating a second redundant word line of an array if a second normal word line of the array is assigned, by a command external to the redundant refresh circuit, to be activated;
- receiving and retaining a determination indicating that the second redundant word line of the array is to be activated;
- determining that a first redundant word line of the array is required to be refreshed according to the determination indicating that the second redundant word line is to be activated, wherein the first redundant word line is immediately adjacent to the second redundant word line;
- determining that a first normal word line of the array is required to be refreshed in response to the second normal word line being assigned to be activated, wherein the first normal word line is immediately adjacent to the second normal word line;
- and
- either refreshing the first redundant word line according to the determination that the first redundant word line is required to be refreshed, or refreshing the first normal word line according to the determination that the first normal word line is required to be refreshed.
3 more elements
A DRAM circuit, comprising:
- an array including a normal word line, a first redundant word line and a second redundant word line immediately adjacent to the first redundant word line, wherein the second redundant word line is activated if the normal word line is assigned, by a memory controller external to the DRAM circuit, to be activated;
- a redundant refresh circuit configured to determine that the first redundant word line is required to be refreshed in response to the second redundant word line being activated;
- and
- a row decoder configured to, according to the determination of the redundant refresh circuit, refresh the first redundant word line,
- wherein the redundant refresh circuit retains the determination until the redundant refresh circuit receives a signal including a command indicating to refresh a redundant word line immediately adjacent to a redundant word line to be activated, and the redundant refresh circuit provides the determination to the row decoder after the redundant refresh circuit receives the signal.
2 more elements
Dependencies are inferred from the claim text.