Double-polarity memory read
AssigneeIntel Corporation
InventorsInnocenzo Tortorelli, Federico Pio
Life of this patent
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Abstract
Circuits, systems, and methods for double-polarity reading of double-polarity stored data information are described. In one embodiment, a method involves applying a first voltage with a first polarity to a plurality of the memory cells. The method involves applying a second voltage with a second polarity to one or more of the plurality of memory cells. The method involves detecting electrical responses of the one or more memory cells to the first voltage and the second voltage. The method also involves determining a logic state of the one or more memory cells based on the electrical responses of the one or more memory cells to the first voltage and the second voltage.
Claims21
A circuit for accessing an array of memory cells, the circuit comprising:
- access circuitry to:
- apply a first voltage with a first polarity to a plurality of the memory cells, wherein the application of the first voltage with the first polarity includes application of a more positive voltage to a first terminal than to a second terminal of a given memory cell of the array, and
- apply a second voltage with a second polarity to one or more of the plurality of the memory cells, wherein the application of the second voltage with the second polarity includes application of a more positive voltage to the second terminal than to the first terminal of the given memory cell of the array;
- and
- sense circuitry to detect electrical responses of the one or more memory cells to the first voltage and the second voltage;
- wherein the access circuitry is to determine a logic state of the one or more memory cells based on the electrical responses of the one or more memory cells to the first voltage and the second voltage.
A system comprising:
- a memory comprising an array of memory cells;
- and
- a circuit communicatively coupled with the array of memory cells, the circuit comprising:
- access circuitry to:
- apply a first voltage with a first polarity to a plurality of the memory cells, wherein the application of the first voltage with the first polarity includes application of a more positive voltage to a first terminal than to a second terminal of a given memory cell of the array, and
- apply a second voltage with a second polarity to one or more of the plurality of memory cells, wherein the application of the second voltage with the second polarity includes application of a more positive voltage to the second terminal than to the first terminal of the given memory cell of the array;
- and
- sense circuitry to detect electrical responses of the one or more memory cells to the first voltage and the second voltage;
- wherein the access circuitry is to determine a logic state of the one or more memory cells based on the electrical responses of the one or more memory cells to the first voltage and the second voltage.
A method of accessing an array of memory cells, the method comprising:
- applying a first voltage with a first polarity to a plurality of the memory cells, wherein applying the first voltage with the first polarity includes applying a more positive voltage to a first terminal than to a second terminal of a given memory cell of the array;
- applying, to one or more of the plurality of memory cells, a second voltage with a second polarity, wherein applying the second voltage with the second polarity includes applying a more positive voltage to the second terminal than to the first terminal of the given memory cell of the array;
- detecting electrical responses of the one or more memory cells to the first voltage and the second voltage;
- and
- determining a logic state of the one or more memory cells based on the electrical responses of the one or more memory cells to the first voltage and the second voltage.
Dependencies are inferred from the claim text.