Wireline receiver circuitry having collaborative timing recovery

An apparatus comprising:

• a first receiver lane including a first decision feedback equalizer (DFE) to sample a first input signal based on first clock signals and generate a first data information and a first phase error information;
• a second receiver lane including a second DFE to sample a second input signal based on second clock signals and generate a second data information and a second phase error information;
• and
• a control unit to generate control information based on the first phase error information and the second phase error information, the first receiver lane to control phases of the first clock signals based on the control information, and the second receiver lane to control phases of the second clock signals based on the control information, wherein:
• the first receiver lane is to provide a first additional control information based on the first phase error information, and to select one of the control information and the first additional control information to generate a first selected control information in order to control timing of the first clock signals based on the first selected control information;
• and
• the second receiver lane is to provide a second additional control information based on the second phase error information, and to select one of the control information and the second additional control information to generate a second selected control information in order to control timing of the second clock signals based on the second selected control information.

An apparatus comprising:

• an input to receive an input signal;
• additional inputs to receive clock signals having different phases to sample the input signal;
• and
• a decision feedback equalizer (DFE) including a first DFE slice coupled to the input node, and a second DFE slice coupled to the input node, the DFE including a number of data comparators and a number of phase error comparators, wherein:
• the first DFE slice includes a first summer including a first summer output node, first comparators of the number of data comparators and at least one phase error comparator of the number of phase error comparators, each comparator of the first comparators includes an input node coupled to the first summer output node, the at least one phase error comparator includes an input node coupled to the first summer output node, and the quantity of the least one first phase error comparator of the first DFE slice is not greater than a quantity of the first comparators;
• and
• the second DFE slice includes a second summer including a second summer output node, second comparators of the number of data comparators and at least one second phase error comparator of the number of phase error comparators, each comparator of the second comparators includes an input node coupled to the second summer output node, the at least one second phase error comparator includes an input node coupled to the second summer output node, and the quantity of the least one second phase error comparator is not greater than a quantity of the second comparators.

A method comprising:

• sampling a first input signal based on first clock signals to generate a first data information and a first phase error information, sampling being performed at a first decision feedback equalizer (DFE) of a first receiver lane;
• sampling a second input signal based on second clock signals to generate a second data information and a second phase error information, sampling being performed at a second DFE of a second receiver lane;
• generating control information based on the first phase error information and the second phase error information;
• controlling phases of the first clock signals based on the control information;
• and
• controlling phases of the second clock signals based on the control information, wherein the first phase error information is generated based on values of three consecutive bits of the first data information, and the second phase error information is generated based on values of three consecutive bits of the second data information, and
• the first phase error information is generated based on a first bit of the three consecutive bits of the first data information having a first value, a second bit of the three consecutive bits of the first data information having either the first value or a second value, and a third bit of the three consecutive bits of the first data information having the second value, and the first bit of the three consecutive bits of the first data information is sampled before the second and third bits of the three consecutive bits of the first data information are sampled;
• and
• the second phase error information is generated based on a first bit of the three consecutive bits of the second data information having the first value, a second bit of the three consecutive bits of the second data information having either the first value or the second value, and a third bit of the three consecutive bits of the second data information having the second value, and the first bit of the three consecutive bits of the second data information is sampled before the second and third bits of the three consecutive bits of the second data information are sampled.