Asymmetric on-state resistance driver optimized for multi-drop DDR4
AssigneeIntegrated Device Technology, Inc.
InventorsYue Yu, Craig DeSimone, Al Xuefeng Fang, Yanbo Wang
Life of this patent
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Abstract
An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a memory signal that transfers read data across a read line to a memory controller. The plurality of control registers may be configured to enable one or more of the driver circuits. A pull up strength and a pull down strength of the memory signal may be configured in response to how many of the plurality of driver circuits are enabled. The plurality of driver circuits implement an asymmetric pull up and pull down of the memory signal.
Claims20
An apparatus comprising:
- a plurality of driver circuits configured to drive a read line in response to a memory signal and a reference voltage to transfer read data across said read line to a memory controller;
- and
- a plurality of control registers configured to enable a first number of said driver circuits to operate solely as pull up drivers and a second number of said driver circuits to operate solely as pull down drivers, wherein (a) a pull up strength and a pull down strength of said memory signal is configured in response to how many of said plurality of driver circuits are enabled as said pull up drivers and said pull down drivers, respectively, and (b) said plurality of driver circuits and said plurality of control registers implement an asymmetric voltage swing of said read line about a voltage level that is half of said reference voltage by setting said first number different from said second number.
An apparatus comprising:
- a first plurality of driver circuits configured to provide a pull up strength of a memory signal that transfers read data across a read line to a memory controller;
- a second plurality of driver circuits configured to provide a pull down strength of said memory signal;
- and
- a plurality of control registers configured to enable one or more of said first plurality of driver circuits and one or more of said second plurality of driver circuits, wherein (a) said pull up strength of said memory signal is configured in response to how many of said first plurality of driver circuits are enabled, (b) said pull down strength of said memory signal is configured in response to how many of said second plurality of driver circuits are enabled and (c) different numbers of said first plurality of driver circuits and said second plurality of driver circuits are enabled to implement an asymmetric voltage swing of said memory signal about an internally generated reference voltage.
Dependencies are inferred from the claim text.