Distribution of forwarded clock
AssigneeIntel Corporation
InventorHuimin Chen
Life of this patent
Estimating the term…
Abstract
A source component includes a clock source to generate a clock signal, a plurality of front-end driver circuits to transmit signals to a sink component over a plurality of data lanes of an interconnect, and a clock distribution circuit coupled to the clock source and the plurality of front-end driver circuits. The clock distribution circuit is to distribute a first clock pulse of the clock signal on a first data lane and a second clock pulse of the clock signal on a second data lane. A sink component is to recover the first clock pulse of the clock signal from the first data lane and the second clock pulse of the clock signal from the second data lane, wherein the clock recovery circuit includes clock reconstruction logic to reconstruct the clock signal from the first clock pulse and the second clock pulse.
Claims25
A source component comprising:
- a clock source to generate a clock signal;
- a plurality of front-end driver circuits to transmit signals to a sink component over a plurality of data lanes of an interconnect;
- and
- a clock distribution circuit coupled to the clock source and the plurality of front-end driver circuits, wherein the clock distribution circuit is to distribute a first clock pulse of the clock signal on a first data lane of the plurality of data lanes and a second clock pulse of the clock signal on a second data lane of the plurality of data lanes.
A sink component comprising:
- a plurality of front-end receiver circuits to receive signals from a source component over a plurality of data lanes of an interconnect;
- and
- a clock recovery circuit coupled to the plurality of front-end receiver circuits and to recover a first clock pulse of a clock signal from a first data lane of the plurality of data lanes and to recover a second clock pulse of the clock signal from a second data lane of the plurality of data lanes, wherein the clock recovery circuit includes clock reconstruction logic to reconstruct the clock signal from the first clock pulse and the second clock pulse.
A method comprising:
- sequentially distributing, by a source component to a sink component and without data, a plurality of sequential clock pulses of a clock signal across a plurality of data lanes of an interconnect between the source component and the sink component;
- in response to the sink component reconstructing the clock signal from the plurality of sequential clock pulses recovered from the plurality of data lanes, transmitting a clock distribution pattern by the source component to the sink component over at least one of the plurality of data lanes;
- and
- distributing with data, by the source component according to the clock distribution pattern, a first clock pulse of the clock signal on a first data lane of the plurality of data lanes and a second clock pulse of the clock signal on a second data lane of the plurality of data lanes.
A method comprising:
- transmitting, by a source component to a sink component over an interconnect having a plurality of data lanes and after clock synchronization, a clock distribution pattern that defines a pseudo-random distribution of a plurality of sequential clock pulses of a clock signal from the source component to the sink component;
- and
- pseudo-randomly distributing, by the source component while transmitting data to the sink component over the plurality of data lanes, the plurality of sequential clock pulses of the clock signal across the plurality of data lanes according to the clock distribution pattern.
Dependencies are inferred from the claim text.