Analog-to-digital converter, electronic device, and method of controlling analog-to-digital converter

An electronic device comprising:

• an oscillator that generates an oscillation signal having a cycle that depends on a signal level of an input analog signal;
• a current bit generation unit that generates, as a current bit, a bit indicating a value of the oscillation signal at each of a plurality of timings within the cycle;
• a delay unit that delays each current bit over a predetermined period and supplies the delayed current bit as a delayed bit;
• a determination unit that determines whether a change amount of a phase of the oscillation signal changed within the predetermined period is greater than a half cycle of the cycle;
• an output unit that generates and outputs data indicating a period in which respective values of the current bit and the delayed bit form a specific combination when the change amount is not greater than the half cycle, and generates and outputs data indicating a period in which the respective values of the current bit and the delayed bit are the same or form the specific combination when the change amount is greater than the half cycle;
• and
• a processing unit that processes the data.

A method of controlling an analog-to-digital converter, the method comprising:

• an oscillation step of generating, by an oscillator, an oscillation signal having a cycle that depends on a signal level of an input analog signal;
• a current bit generation step of generating, as a current bit by a current bit generation unit, a bit indicating a value of the oscillation signal at each of a plurality of timings within the cycle;
• a delay step of delaying, by a delay unit, each current bit over a predetermined period and supplying the delayed current bit as a delayed bit;
• a determination step of determining, by a determination unit, whether a change amount of a phase of the oscillation signal changed within the predetermined period is greater than a half cycle of the cycle;
• and
• an output step of generating and outputting, by an output unit, data indicating a period in which respective values of the current bit and the delayed bit form a specific combination when the change amount is not greater than the half cycle, and generating and outputting data indicating a period in which the respective values of the current bit and the delayed bit are the same or form the specific combination when the change amount is greater than the half cycle.