Distributed multi-phase clock generator having coupled delay-locked loops
AssigneeMicrosoft Technology Licensing, LLC
InventorAlan Fiedler
Life of this patent
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Abstract
Multiple, distributed, clock generating delay-locked loop (DLL) elements are interconnected/coupled in such a way as to reduce the amount of phase error present in the clocks output by these DLL elements. A plurality of DLL elements are interconnected/coupled such that a root input clock is successively relayed down a series of DLL elements. The output clocks from each of these DLL elements are interconnected/coupled to phase-corresponding output clocks from DLL elements in the series. This reduces the amount of phase error on these output clocks when compared to DLL elements that do not have outputs coupled to each other.
Claims20
A multi-phase clock generator to generate N*M number of output clocks, comprising:
- N number of delay-locked loop elements, each delay-locked loop element having a root clock input and a root clock output, the N delay-locked loop elements being numbered n=1 to N in order of ascending phase at the root clock input;
- for each delay-locked loop element, the root clock output of the delay-locked loop element numbered n is coupled to the root clock input of the delay-locked loop element numbered n+1, except when n=N;
- the root clock input of the delay-locked loop element numbered n=1 receives a master input clock;
- each delay-locked loop element is configured to produce M number of output clocks;
- N is an integer greater than one;
- M is an even integer greater than three;
- each of the M output clocks of a respective delay-locked loop element has a phase;
- the M output clocks are numbered m=1 to M in order of ascending phase;
- the phase of a respective output clock numbered m+1 substantially equals the phase of a respective output clock numbered m plus 360/M degrees;
- each respective output clock numbered m of the respective delay-locked loop element numbered n is coupled to output clock numbered m-1 of delay-locked loop element numbered n+1, except that when m=1 the respective output clock numbered m=1 is coupled to the output clock numbered m=M of delay-locked loop element numbered n+1;
- and,
- the phase of a respective root clock output substantially equals the phase of a respective root clock input plus 360/M degrees.
A distributed multi-phase clock generator, comprising:
- a first delay-locked loop element to receive a master input clock and to produce a first set of at least M number of output clocks, the first set of output clocks to be delay-locked to the master input clock such that the master input clock is divided into M number of time intervals;
- a second delay-locked loop element to receive a second input clock from the first delay-locked loop element, the second delay-locked loop element to produce a second set of at least M output clocks, the second set of output clocks to be delay-locked to the second input clock such that the second input clock is divided into M time intervals, the second input clock to correspond to the master input clock delayed by one of the M time intervals;
- and,
- coupling between respective ones of the first set of output clocks and the second set of output clocks, the coupling configured such that the first set of output clocks are each coupled to the second set of output clocks such that output clocks with corresponding phase are coupled together.
A method of generating distributed multi-phase output clocks, comprising:
- providing a master input clock to a root clock input of a first delay-locked loop element;
- adjusting a first delay of P delay cells of the first delay-locked loop element to produce a first set of M output clocks that divide the master input clock into 360/M degree intervals;
- delaying the master input clock by the 360/M degree interval to produce a first root clock output from the first delay-locked loop element;
- providing the first root clock output to a root clock input of a second delay-locked loop element;
- adjusting a second delay of P delay cells of the second delay-locked loop element to produce a second set of M output clocks that divide the first root clock output into 360/M degree intervals;
- and,
- coupling the first set of M output clocks to the second set of M output clocks such that at least one of the first set of M output clocks is coupled to one of the second set of M output clocks that has the same number of 360/M intervals of delay from the master input clock.
Dependencies are inferred from the claim text.