US 9,793,894 B1Granted

Data synchronizer for registering a data signal into a clock domain

AssigneeVia Alliance Semiconductor Co., Ltd.

InventorJames R. Lundberg

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Abstract

A data synchronizer that registers an input data signal into a clock domain of a clock signal. The data synchronizer includes in input circuit, first and second pass gates, first and second inverters, gate controller, and a register. The input circuit drives first and second data nodes to opposite logic states based on the input data signal. Each pass gate is coupled between a data node and a capture node. The inverters are cross-coupled between the capture nodes. The gate controller is capable of keeping the pass gates at least partially open during a metastable condition of the capture nodes, and closes the pass gates when the capture nodes resolve to opposite logic states. The register registers a capture node to provide a registered data output in response to the clock signal. The data synchronizer may be implemented using FinFET devices.

Claims21

Dependent claims

A data synchronizer that registers an input data signal into a clock domain of a clock signal, comprising:

an input circuit having an input for receiving the input data signal, having a first output coupled to a first data node and a second output coupled to a second data node, wherein said first and second data nodes are driven to opposite logic states;
a first pass gate having current terminals coupled between said first data node and a first capture node and having positive and negative control terminals;
a second pass gate having current terminals coupled between said second data node and a second capture node and having positive and negative control terminals;
first and second inverters that are cross-coupled between said first and second capture nodes;
a gate controller responsive to the clock signal, having inputs coupled to said first and second capture nodes and outputs coupled to said positive and negative control terminals of said first and second pass gates, wherein said gate controller is capable of keeping said first and second pass gates at least partially open during a metastable condition of said first and second capture nodes, and is capable of closing said first and second pass gates when said first and second capture nodes resolve to opposite logic states;
and
a register that registers at least one of said first and second capture nodes to provide a registered data output in response to the clock signal.

4 more elements

A method of synchronizing an input data signal with a clock signal, comprising:

providing first and second data signals that transition to opposite logic states in response to transitions of the input data signal;
passing the first data signal through a first pass gate to a first capture node;
passing the second data signal through a second pass gate to a second capture node;
in response to an operative transition of the clock signal for latching the first and second capture nodes:
keeping the first and second pass gates at least partially open during a metastable condition of the first and second capture nodes;
and
closing the first and second pass gates to latch the capture nodes when the first and second capture nodes settle to opposite logic states;
and
registering at least one of the first and second capture nodes in response to the clock signal to provide a registered data signal that is synchronous with the clock signal.

6 more elements

Dependencies are inferred from the claim text.