Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals

An apparatus, comprising:

• a clock generator circuit configured to provide first and second clock signals responsive to an input clock signal;
• a duty phase interpolator circuit coupled to the clock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals, the first and second duty cycle corrected interpolated clock signals approximately 180 degrees out of phase relative to one another;
• a duty cycle adjuster circuit coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected clock signal responsive thereto, and further configured to adjust a duty cycle responsive to adjustment signals, wherein the duty cycle adjuster circuit comprises:
• a plurality of adjustable inverter drivers, an adjustable inverter driver of the plurality of adjustable inverter drivers configured to be adjusted to change a timing of an input signal and provide an adjustable inverter driver output signal;
• and
• a plurality of inverters coupled to the plurality of adjustable inverter drivers, an inverter of the plurality of inverters configured to invert an input signal to provide an inverter output signal;
• and
• a duty cycle detector coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to the duty cycle adjuster circuit to adjust the duty cycle to correct the duty cycle error.

A method, comprising:

• providing first and second clock signals;
• responsive to the first clock signal, providing first and second split clock signals, the first and second split clock signals complementary to one another;
• responsive to the second clock signal, providing third and fourth split clock signals, the third and fourth split clock signals complementary to one another;
• interpolating the first and fourth split clock signals to provide a first duty cycle corrected interpolated clock signal;
• interpolating the second and third split clock signals to provide a second duty cycle corrected interpolated clock signal, the first and second duty cycle corrected interpolated clock signals approximately 180 degrees out of phase relative to one another;
• and
• adjusting a duty cycle of at least one of the first and second duty cycle corrected interpolated clock signals to provide a duty cycle corrected output clock signal.

An apparatus, comprising:

• a clock generator circuit configured to provide first and second clock signals responsive to an input clock signal, the second clock signal being approximately 180 degrees out of phase with the first clock signal;
• a duty phase interpolator circuit coupled to the clock generator circuit, the duty phase interpolator circuit comprising first and second phase splitter circuits and a first phase interpolator circuit,
• the first phase splitter circuit configured to receive the first clock signal and provide a first split clock signal and a second split clock signal responsive to the first clock signal, the first and second split clock signals complementary to one another;
• the second phase splitter circuit configured to receive the second clock signal and provide a third split clock signal and a fourth split clock signal responsive to the second clock signal, the third and fourth split clock signals complementary to one another;
• the first phase interpolator circuit coupled to the first and second phase splitter circuits and configured to receive the first and fourth split clock signals and provide a first duty cycle corrected interpolated clock signal responsive thereto.