Flip-flop with zero-delay bypass mux
AssigneeSamsung Electronics Co., Ltd.
InventorsChristina Wells, Matthew Berzins, Min Su Kim
Life of this patent
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Abstract
Exemplary embodiments may disclose a flip-flop circuit for inserting a zero-delay bypass mux including a master circuit which is configured to receive a data input, an input clock signal, and a bypass signal, and output an intermediate signal to a first node; and a slave circuit which is configured to receive the intermediate signal at the first node, the input clock signal, and the bypass signal, and output an output clock signal. The bypass signal controls the slave circuit to output one of a buffered input clock signal and a stretched clock signal as the output clock signal based on a logic level of the bypass signal.
Claims17
A flip-flop circuit for inserting a zero-delay bypass mux comprising:
- a master circuit which is configured to receive a data input, an input clock signal, and a bypass signal, and output an intermediate signal to a first node;
- and
- a slave circuit which is configured to receive the input clock signal simultaneously with the bypass signal, to receive the intermediate signal at the first node, and to output an output clock signal,
- wherein in response to a logic level of the bypass signal being set at high, the master circuit is disabled, the intermediate signal is forced logic high, the input clock signal is buffered, and the buffered input clock signal is output as the output clock signal from the slave circuit.
A method of inserting a zero-delay bypass mux, the method comprising:
- receiving a data input, an input clock signal, and a bypass signal at a first circuit;
- outputting an intermediate signal to a first node of the first circuit;
- receiving the input clock signal simultaneously with the bypass signal at a second circuit, and receiving the intermediate signal at the first node at the second circuit;
- and
- outputting an output clock signal from the second circuit;
- disabling the first circuit during a bypass mode;
- forcing the intermediate signal to logic high during the bypass mode;
- buffering the input clock signal in the second circuit during the bypass mode;
- and
- outputting a buffered input clock signal as the output clock signal from the second circuit during the bypass mode,
- wherein the bypass mode is a mode in which a logic level of the bypass signal is set at high.
A flip-flop circuit comprising:
- a first circuit which receives an input clock signal and outputs an intermediate signal;
- and
- a second circuit which receives the input clock signal simultaneously with a bypass signal, receives the intermediate signal, and outputs an output clock signal,
- wherein the first circuit comprises:
- a bypass PMOS transistor connected between a voltage source and a first PMOS transistor, and controlled by the bypass signal, and
- a bypass NMOS transistor connected between a first NMOS and ground, and controlled by the bypass signal,
- wherein the second circuit comprises:
- a bypass NOR gate which is configured to receive the bypass signal and a signal of a first node and output a signal of a second node, and
- an inverter which inverts a signal of the first node such that the inverter outputs an output clock signal,
- wherein the signal of the second node is a control input to a second PMOS transistor and a second NMOS transistor of the second circuit,
- wherein in response to a logic level of the bypass signal being set at high, the first circuit is disabled, the intermediate signal is forced logic high, the input clock signal is buffered, and the buffered input clock signal is output as the output clock signal from the second circuit.
Dependencies are inferred from the claim text.