Circuits and methods for controlling a three-level buck converter

A method for controlling a three-level buck converter, the method comprising:

• receiving a first clock and a second clock, wherein the second clock is a phase-shifted version of the first clock;
• producing first and second ramp signals based on the first and second clocks, respectively;
• receiving the first ramp signal at the first comparator and receiving the second ramp signal at the second comparator;
• at the first comparator, generating a first pulse width modulated signal from the first ramp signal;
• at the second comparator, generating a second pulse width modulated signal from the second ramp signal;
• and
• outputting the first pulse width modulated signal to a first subset of input switches of the three-level buck converter and outputting the second pulse width modulated signal to a second subset of input switches of the three-level buck converter;
• and
• producing a third pulse width modulated signal and a fourth pulse width modulated signal to control an additional three-level buck converter, wherein the third and fourth pulse width modulated signals are phase-shifted relative to the first and second pulse width modulated signals by 90°.

A voltage regulating circuit comprising:

• a three-level buck converter having four input switches, a first subset of the four input switches configured to receive a first pulse width modulated signal, a second subset of the four input switches configured to receive a second pulse width modulated signal;
• a pulse width modulated signal controller in communication with the three-level buck converter and configured to provide the first and second pulse width modulated signals, the pulse width modulated signal controller comprising:
• an error circuit configured to receive an output voltage of the three-level buck converter and a reference signal and configured to output an error signal;
• a ramp generating circuit configured to receive a first clock and a second clock, the second clock being a phase-shifted version of the first clock, the ramp generating circuit configured to generate a first and a second ramp signal from the first and second clock, respectively;
• a first comparator configured to receive the error signal and the first ramp signal and to output the first pulse width modulated signal in response thereto;
• and
• a second comparator configured to receive the error signal and the second ramp signal and to output the second pulse width modulated signal in response thereto;
• the voltage regulating circuit further comprising an additional pulse width modulated signal controller configured to control an additional three-level buck converter, wherein the additional pulse width modulated signal controller is configured to generate a third and a fourth clock for the another three-level buck converter, further wherein the third and fourth clocks are phase-shifted 90° with respect to the first and second clocks.

A circuit comprising:

• a three-level buck converter;
• and
• a pulse width modulated signal controller configured to control the three-level buck converter, the pulse width modulated signal controller including:
• means for producing a first ramp signal from a first clock signal and a second ramp signal from a second clock signal, wherein the second clock signal is a phase-shifted version of the first clock signal;
• means for generating the first pulse width modulated signal from the first ramp signal;
• and
• means for generating the second pulse width modulated signal from the second ramp signal;
• wherein the means for generating the first pulse width modulated signal and the means for generating the second pulse width modulating signal are configured to generate the first and second pulse width modulated signals in response to a level of a voltage output of the three-level buck converter;
• the circuit further comprising an additional pulse width modulated signal controller for an additional three-level buck converter, wherein the additional pulse width modulated signal controller is configured to receive a third clock signal and a fourth clock signal, further wherein the fourth clock signal is a phase-shifted version of the third clock signal, and wherein the first and second clock signals are phase-shifted relative to the third and fourth clock signals by 90°.