Fin field effect transistor (FinFET)

A fin field effect transistor (FinFET) comprising:

• a fin having an upper portion and a lower portion extending above a substrate, the upper portion being doped with a dopant of a first conductivity type, the lower portion being doped with a dopant of a second conductivity type different from the first conductivity type, and a junction between the upper portion and the lower portion acts as a diode;
• at least one layer of high-k dielectric material adjacent to at least one side of the fin, wherein the high-k dielectric material extends in a first plane parallel to the fin and does not extend in a second plane in perpendicular to the fin, wherein the second plane is at a bottom plane of the fin;
• a shallow trench isolation layer provided above the substrate and adjacent to the layer of high-k dielectric material, wherein a portion of the high-k dielectric material covers the junction and the portion of the high-k dielectric material is embedded in the shallow trench isolation layer;
• a gate region formed on top of and around the sides of the fin;
• a channel region formed below the gate region;
• and
• a punch through stopper layer provided in the lower portion of the fin below the channel region.

A method of fabricating a fin field effect transistor (FinFET), the method comprising the steps of:

• etching (s4) the substrate to provide a fin extending above a substrate, wherein the fin has an upper portion and a lower portion, the upper portion being doped with a dopant of a first conductivity type, the lower portion being doped with a dopant of a second conductivity type different from the first conductivity type, wherein a junction between the upper portion and the lower portion acts as a diode;
• depositing (s6) a layer of high-k dielectric material adjacent to at least one side of the fin, wherein the high-k dielectric material extends in a first plane parallel to the fin and does not extends in a second plane in perpendicular to the fin, wherein the second plane is at a bottom plane of the fin;
• depositing (s8) a shallow trench isolation layer above the substrate and adjacent to the layer of high-k dielectric material, wherein the junction is between a top surface of the shallow trench isolation layer and a bottom surface of the shallow trench isolation layer;
• providing (s10) a gate region on top of and around the sides of the fin;
• and
• implanting dopants (s12) in the fin to form the active semiconductor areas.