Silicon germanium p-channel FinFET stressor structure and method of making same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsueh-Chang Sung, Liang-Yi Chen
Life of this patent
Estimating the term…
Abstract
A source/drain (S/D) structure includes a SiGe structure epitaxially grown and having sloped facets on a recessed fin structure disposed adjacent to a channel portion of a finFET, a first Ge structure having a rounded surface epitaxially grown on the SiGe structure, and a capping layer formed over the rounded surface of the Ge structure. The capping layer may be formed of Si. Such S/D structures provide both a larger physical size for lower contact resistance, and greater volume and concentration of Ge for higher compressive strain applied to the channel portion of the finFET.
Claims20
A method of forming source/drain (S/D) structures for a finFET, comprising:
- forming a fin on a semiconductor substrate, the fin extending above a top surface of an adjacent isolation structure;
- forming a gate stack on the fin, the gate stack having a first sidewall and a second sidewall;
- forming a first sidewall spacer adjacent the first sidewall, and a second sidewall spacer adjacent the second sidewall;
- etching portions of the fin not covered by the gate stack and not covered by the sidewall spacers;
- epitaxially growing SiGe on the etched portions of the fin;
- and
- epitaxially growing Ge on the epitaxially grown SiGe, wherein the epitaxially grown Ge does not contact the adjacent isolation structure,
- wherein the epitaxially grown SiGe has sloped surfaces, and the epitaxially grown Ge has a rounded surface.
A method of applying compressive stress to a channel region of a p-channel finFET, comprising:
- forming a gate stack on a fin, the gate stack having a first sidewall and a second sidewall, the fin extending above a top surface of an adjacent isolation structure;
- forming a first sidewall spacer along the first sidewall and a second sidewall spacer along the second sidewall;
- etching portions of the fin not covered by the gate stack or the sidewall spacers to provide source/drain (S/D) foundation structures;
- epitaxially growing SiGe on the S/D foundation structures to form a diamond-shaped structure on each of the S/D foundation structures;
- epitaxially growing Ge on each of the diamond-shaped structures to form a rounded structure, wherein the epitaxially grown Ge does not contact the adjacent isolation structure;
- and
- forming a capping layer on each of the rounded structures.
A method of fabricating a semiconductor device, comprising:
- forming a fin on a semiconductor substrate;
- forming a gate stack on the fin, the gate stack having a sidewall, the fin extending above a top surface of an adjacent isolation structure;
- forming a sidewall spacer adjacent the sidewall;
- etching portions of the fin not covered by the gate stack and not covered by the sidewall spacer;
- epitaxially growing SiGe on the etched portions of the fin;
- and
- epitaxially growing Ge on the epitaxially grown SiGe, wherein the epitaxially grown Ge does not contact the adjacent isolation structure,
- wherein the epitaxially grown SiGe has sloped surfaces, and the epitaxially grown Ge has a rounded surface.
Dependencies are inferred from the claim text.