Semiconductor device having insulating pattern and method of forming the same

A semiconductor device, comprising:

• a plurality of device isolation layers defining an active area on a substrate;
• a plurality of gate electrodes crossing the active area and the device isolation layer;
• spacers on side surfaces of each of the plurality of gate electrodes;
• trenches in the active area on either side of the gate electrodes crossing the active area;
• a stressor in each trench, each stressor comprising a first semiconductor layer formed along a sidewall of the stressor, a second semiconductor layer formed within the trench on the first semiconductor layer and a third semiconductor layer formed on the second semiconductor layer, the first, second and third-semiconductor layers being different from each other;
• a cavity between the second semiconductor layer of each trench and the device isolation layer, and aligned under the spacers;
• and
• an insulating pattern in the cavity, the insulating pattern being disposed at least partially under a lower portion of an adjacent gate electrode,
• wherein the insulating pattern is disposed between the spacer on the side surface of one of the plurality of gate electrodes and the stressor and between the one of the plurality of gate electrodes and the device isolation layer to vertically overlap a lower portion of the one of the plurality of gate electrodes, and
• wherein a bottom of the third semiconductor layer is disposed at a level equal to or higher than an upper end of the active area.

A semiconductor device, comprising:

• a device isolation layer defining an active area on a substrate;
• a first gate electrode crossing the active area;
• a second gate electrode crossing the device isolation layer;
• a first gate dielectric layer surrounding bottoms and side surfaces of the first gate electrode;
• a second gate dielectric layer surrounding bottoms and side surfaces of the second gate electrode;
• spacers on the side surfaces of the first gate electrode and the second gate electrode;
• a trench in the active area between the first gate electrode and the second gate electrode;
• a stressor in the trench, the stressor comprising a first semiconductor layer formed along a sidewall of the stressor, a second semiconductor layer formed within the trench on the first semiconductor layer and a third semiconductor layer formed on the second semiconductor layer;
• a cavity between the stressor and the device isolation layer and adjacent to the second gate electrode;
• and
• an insulating pattern in the cavity,
• wherein the insulating pattern is disposed between the spacer on the side surface of the second gate electrode and the stressor and between the second gate electrode and the device isolation layer to vertically overlap a lower portion of the second gate electrode;
• wherein the insulating pattern contacts at least one of the spacers and the second gate dielectric layer, and
• wherein the first semiconductor layer contains a first amount of Ge and the second semiconductor layer contains a second amount of Ge that is greater than the first amount of Ge and the third semiconductor layer contains a third amount of Ge that is less than the first amount of Ge.