Method and structure of making enhanced UTBB FDSOI devices
AssigneesSTMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SAS
InventorsQing Liu, Thomas Skotnicki
Life of this patent
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Abstract
An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.
Claims20
A method, comprising:
- forming a first semiconductor layer on a second semiconductor layer;
- forming a trench having first and second portions through the first semiconductor layer and at least into the second semiconductor layer, the forming the trench including exposing top and side surfaces of the first semiconductor layer;
- forming an insulating layer in the first and second portions of the trench, the insulating layer having a top surface that is below a bottom surface of the first semiconductor;
- and
- forming a gate structure on the top and side surfaces of the first semiconductor layer, the forming of the gate structure including forming a first portion on the top surface of the first semiconductor layer and second portions that extend into the first and second portions of the trench.
A method, comprising:
- forming an elongated channel by:
- forming a first trench and a second trench through a first semiconductor layer, a first insulating layer, and a second semiconductor layer;
- forming a second insulating layer in the first trench and the second trench, a top surface of the second insulating layer being below a bottom surface of the first semiconductor layer;
- and
- forming a gate structure on the first semiconductor layer, the gate structure having a first portion that is on a top surface of the first semiconductor layer and a second portion that extends into the first trench and the second trench, the second portion extending past the bottom surface of the first semiconductor layer.
A method, comprising:
- forming a semiconductor layer on a first insulating layer that is on a substrate;
- exposing a top surface of the semiconductor layer, side surfaces of the semiconductor layer, and side surfaces of the first insulating layer, the side surfaces of the semiconductor layer have a first length extending away from the substrate, the top surface having a second length that is transverse to the first length, the second length being significantly larger than the first length;
- and
- forming a gate structure overlapping a portion of the top surface of the semiconductor layer, portions of a first one and a second one of the side surfaces of the semiconductor layer, and portions of a first one and a second one of the side surfaces of the first insulating layer.
Dependencies are inferred from the claim text.