Apparatus and method of fabrication for GaN/Si transistors isolation

A method of fabricating gallium nitride (GaN) transistors on a silicon on insulator (SOI) wafer with a GaN transistor in a first transistor circuit having its substrate isolated from the substrate of a transistor in a second transistor circuit, the method comprising:

• fabricating an isolated first silicon region and an isolated second silicon region on a SOI wafer comprising an insulator layer and a silicon layer disposed over the insulator layer, each of the first silicon region and the second silicon region bounded on its sides by a trench filled with insulator material so as to define a first cavity over the isolated first silicon region and a second cavity over the isolated second silicon region;
• fabricating a first active area within the first cavity over the isolated first silicon region and fabricating a second active area within the second cavity over the isolated second silicon region through epitaxial growth operations to respectively form the first transistor circuit and the second transistor circuit, the first active area comprising a first GaN layer;
• and
• fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.

A method of fabricating a semiconductor device on a silicon on insulator (SOI) wafer comprising a silicon layer and an insulator layer, the method comprising:

• fabricating an isolated first silicon region and an isolated second silicon region, the first and second isolated silicon regions each formed from the silicon layer and separated from one another by a trench above the insulator layer;
• filling the trench with an insulator that bounds respective sides of the isolated first and second silicon regions such that the first silicon region is isolated from the second silicon region by the insulator material and a cavity respectively is disposed over each of the first and second silicon regions;
• after filling the trench, respectively fabricating first and second active regions comprising first and second GaN layers within the cavities to form the first transistor circuit and the second transistor circuit to form the first transistor circuit and the second transistor circuit;
• and
• providing a respective body contact connection point for each of the first transistor circuit and the second transistor circuit.