Tunneling field effect transistor and methods of making such a transistor
AssigneeGlobalfoundries Inc.
InventorBartlomiej Jan Pawlak
Life of this patent
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Abstract
One illustrative method of forming a TFET device includes forming a first semiconductor material that extends for a full length of a drain region, a gate region and a source region of the device, masking the drain region while exposing at least a portion of the gate region and exposing the source region, forming a second semiconductor material above the gate region and above the source region, forming a third semiconductor material above the second semiconductor material and above the gate region and above the source region, the third semiconductor material being doped with an opposite type of dopant material than in the first semiconductor material, masking the drain region, and forming a gate structure above at least a portion of the exposed gate region.
Claims28
A method of forming a tunneling field effect transistor device comprising a drain region, a source region, a gate region and a gate structure, the method comprising:
- forming a first semiconductor material above a semiconductor substrate, said first semiconductor material being doped with a first type of dopant material, said first semiconductor material extending a full length of said drain region, said gate region and said source region, wherein said first semiconductor material is part of said drain region;
- forming a first masking layer that masks said drain region but exposes at least a portion of said gate region and exposes said source region;
- with said first masking layer in position, forming a second semiconductor material above at least a portion of said gate region and above said source region, wherein said second semiconductor material defines said channel region;
- with said first masking layer in position, forming a third semiconductor material above said second semiconductor material and above at least a portion of said gate region and above said source region, said third semiconductor material being doped with a second type of dopant material that is opposite to said first type of dopant material, wherein said third semiconductor material is part of said source region;
- with said first masking layer in position, forming a second masking layer that masks said drain region but exposes at least a portion of said gate region;
- and
- forming a gate structure above at least a portion of said exposed gate region.
A method of forming a tunneling field effect transistor device comprising a drain region, a source region, a gate region and a gate structure, the method comprising:
- forming a fin in a semiconductor substrate;
- removing at least a portion of said fin so as to define a fin cavity bounded, at least in part, by insulating material positioned adjacent said fin;
- forming a band-offset buffer semiconductor material within said fin cavity;
- forming a first semiconductor material on said band-offset buffer semiconductor material within said fin cavity, said first semiconductor material being doped with a first type of dopant material, said first semiconductor material extending a full length of said drain region, said gate region and said source region;
- forming a first masking layer that masks said drain region but exposes at least a portion of said gate region and exposes said source region;
- with said first masking layer in position, forming a second semiconductor material on said first semiconductor material and above at least a portion of said gate region and above said source region;
- with said first masking layer in position, forming a third semiconductor material on said second semiconductor material and above at least a portion of said gate region and above said source region, said third semiconductor material being doped with a second type of dopant material that is opposite to said first type of dopant material;
- with said first masking layer in position, forming a second masking layer that masks said drain region but exposes at least a portion of said gate region;
- and
- forming a gate structure above at least a portion of said exposed gate region.
A method of forming a tunneling field effect transistor device comprising a drain region, a source region, a gate region and a gate structure, the method comprising:
- forming a first semiconductor material above a semiconductor substrate, said first semiconductor material being doped with a first type of dopant material, said first semiconductor material extending a full length of said drain region, said gate region and said source region;
- forming a first masking layer that masks said drain region but exposes at least a portion of said gate region and exposes said source region;
- with said first masking layer in position, forming a second semiconductor material above at least a portion of said gate region and above said source region;
- with said first masking layer in position, forming a third semiconductor material above said second semiconductor material and above at least a portion of said gate region and above said source region, said third semiconductor material being doped with a second type of dopant material that is opposite to said first type of dopant material;
- with said first masking layer in position, forming a second masking layer that masks said drain region but exposes at least a portion of said gate region;
- and
- forming a replacement gate structure above at least a portion of said exposed gate region.
Dependencies are inferred from the claim text.