Fin field effect transistor device with reduced overlap capacitance and enhanced mechanical stability

A semiconductor device comprising:

• a silicon substrate;
• an epitaxial silicon layer over the silicon substrate and having lower portions, upper portions, and intermediate portions, contiguous with and between the lower and upper portions, and having a transitional upper surface set at an angle with respect to upper surfaces of the lower and upper portions;
• an array of isolation structures between the epitaxial silicon layer and the silicon substrate;
• an array of semiconductor fins, comprising:
• channels of substantially uniform thickness being defined in the upper portions of said epitaxial silicon layer and being over and aligned with said array of isolation structures;
• source regions of substantially uniform thickness in the lower and intermediate portions of the epitaxial silicon layer;
• drain regions of substantially uniform thickness in the lower and intermediate portions of said epitaxial silicon layer;
• a gate over the channels of the array of semiconductor fins, the gate configured to control current flow within the channels in response to an applied voltage;
• and
• epitaxial silicon-germanium raised sources and drains over the source regions and drain regions, respectively.

A semiconductor device comprising:

• a silicon substrate;
• an epitaxial silicon layer over the silicon substrate, the epitaxial silicon layer having lower portions, upper portions, and intermediate portions being contiguous with and between the lower and upper portions and having a transitional upper surface set at an angle with respect to upper surfaces of the lower and upper portions;
• an array of isolation structures between the upper portions layer and the silicon substrate;
• an array of semiconductor fins including:
• channels of substantially uniform thickness being defined in the upper portions of said epitaxial silicon layer and being over and aligned with said array of isolation structures;
• and
• sources and drains of substantially uniform thickness being defined in the lower and intermediate portions of said epitaxial silicon layer;
• a gate over the channels of the array of semiconductor fins, the gate configured to control current flow within the array of semiconductor fins in response to an applied voltage;
• and
• epitaxial silicon-germanium source and drain layers over the source and drain, respectively, and including doped source and drain structures extending above the silicon substrate.

A FinFET, comprising:

• a silicon substrate;
• a fin extending above the silicon substrate, the fin including:
• a patterned oxide layer;
• a blanket semiconductor layer overlying the patterned oxide layer, the blanket semiconductor layer having lower portions, upper portions, intermediate portions between the lower and upper portions, and a transitional upper surface set at an angle with respect to upper surfaces of the lower and upper portions, the patterned oxide layer positioned between the upper portions and the silicon substrate;
• a source region in one of the lower portions;
• a drain region in one of the lower portions;
• and
• a channel in one of the upper portions;
• and
• a gate that wraps around three sides of the channel.