Back to results
US 9,793,375 B2Granted
High voltage lateral DMOS transistor with optimized source-side blocking capability
AssigneeTexas Instruments Incorporated
InventorsPhilip Leland Hower, Sameer Pendharkar, Marie Denison
Life of this patent
Estimating the term…
Abstract
An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.
Claims18
A method of forming an integrated circuit, comprising:
- receiving a semiconductor wafer having a substrate of a first conductivity type, a buried drift region of a second conductivity type in the substrate, and an epitaxial layer of the first conductivity type on the buried drift region, wherein the second conductivity type opposing the first conductivity type;
- applying a link ion implant mask over the epitaxial layer, the link ion implant mask defining a drain open area over a drain portion of the buried drift region, and a channel open area over a channel portion of the buried drift region and spaced apart from the drain open area;
- and
- implanting dopants through the drain open area and the channel open area onto the epitaxial layer to form a drain link implanted region and a channel link implanted region spaced apart from the drain link implanted region at a top surface of the semiconductor wafer;
- and
- diffusing the dopants in the drain link implanted region to form a drain diffused link extending to the drain portion of the buried drift region;
- and
- diffusing the dopants in the channel link implanted region to form a channel diffused link extending to the channel portion of the buried drift region, the channel diffused link spaced apart from the drain diffused link,
- wherein the top surface including a segment abutting a gate dielectric layer.
6 more elements
A method of forming an extended drain transistor, comprising:
- receiving a semiconductor wafer having a top surface of a first conductivity type and a buried drift region of a second conductivity type under the top surface, wherein the second conductivity type opposing the first conductivity type;
- and
- forming a drain link extending from the top surface to the buried drift region and having dopants of the second conductivity type;
- and
- forming a channel link extending from the top surface to the buried drift region and having the dopants of the second conductivity type, the channel link separated from the drain link by a RESURF region along the top surface,
- wherein the top surface includes a segment abutting a gate dielectric layer.
3 more elements
A method of forming an integrated circuit, comprising:
- forming a buried drift region below a top surface of a semiconductor wafer;
- applying a link ion implant mask over the top surface, the link ion implant mask defining:
- a drain open area over a drain portion of the buried drift region;
- a channel open area over a channel portion of the buried drift region and spaced apart from the drain open area along the top surface;
- and
- an isolation open area over an isolation portion of the buried drift region;
- and
- implanting dopants onto the top surface through the drain open area, the channel open area, and the isolation open area to form a drain link implanted region, a channel link implanted region spaced apart from the drain link implanted region, and an isolation link implanted region laterally surrounding a source region above the buried drift region;
- and
- diffusing the dopants in the drain link implanted region to form a drain diffused link connecting with the drain portion of the buried drift region;
- diffusing the dopants in the channel link implanted region to form a channel diffused link connecting with the channel portion of the buried drift region, the channel diffused link separated from the drain diffused link by a RESURF region of the top surface;
- and
- diffusing the dopants in the isolation link implanted region to form an isolation diffused link connecting with the isolation portion of the buried drift region,
- wherein the top surface includes a segment abutting a gate dielectric layer.
11 more elements
Dependencies are inferred from the claim text.