US 9,793,350 B1Granted

Multiple layer side-gate FET switch

AssigneeNorthrop Grumman Systems Corporation

InventorsRoger S. Tsai, Sumiko L. Poust, Weidong Liu

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Abstract

An exemplary FET includes a base and first and second stacked layer groups each having a nonconductive layer and a semiconductive layer adjacent the nonconductive layer. Source and drain electrodes are in low resistance contact with the semiconductive layers. First and second parallel trenches extend vertically between the source and drain electrodes to create access to first and second edges, respectively, of the layers. A 3-dimensional ridge is defined by the layers between the first and second trenches. A continuous conductive side gate extends generally perpendicular to the trenches and engages the first edges, the top of the ridge and the second edges. A gate electrode is disposed in low resistance contact with the conductive side gate. The figure of merit for the FET increases as the number of layer groups increases. A plurality of parallel spaced apart ridges, all engaged by the same side gate, can be utilized.

Claims20

Dependent claims

A field effect transistor (FET) device comprising:

a base;
a first layer group having a first nonconductive layer adjacent the base and a first semiconductive layer over the first nonconductive layer;
a second layer group having a second nonconductive layer adjacent the first semiconductive layer and a second semiconductive layer over the second nonconductive layer, the second layer group being vertically stacked on the first layer group;
a top nonconductive layer is disposed above a topmost semiconductive layer;
a source electrode in conductive contact with the first and second semiconductive layers;
a drain electrode spaced apart from the source electrode and in conductive contact with the first and second semiconductive layers;
a first trench disposed between the source and drain electrodes that creates access to first edges of at least all semiconductive layers;
a second trench disposed between the source and drain electrodes generally parallel to and spaced apart from the first trench, the second trench creating access to second edges of at least all semiconductive layers;
a 3-dimensional ridge defined by a portion of the first and second layer groups and the top nonconductive layer between the first and second trenches;
a continuous conductive side gate is disposed on the first edges, a top of the 3-dimensional ridge and the second edges generally perpendicular to the first and second trenches;
a gate electrode disposed in conductive contact with the continuous conductive side gate.

8 more elements

A semiconductor implemented radio frequency switch having ON and OFF states comprising:

a base;
a first layer group having a first nonconductive layer adjacent the base and a first semiconductive layer over the first nonconductive layer;
a second layer group having a second nonconductive layer adjacent the first semiconductive layer and a second semiconductive layer over the second nonconductive layer;
a source electrode in conductive contact with the first and second semiconductive layers;
a drain electrode spaced apart from the source electrode and in conductive contact with the first and second semiconductive layers;
a ridge of portions of the first and second layer groups is disposed between the source and drain electrodes, the ridge having a top that connects first and second sides that are generally perpendicular to the top, the first and second sides exposing respective first and second edges of each layer in the second layer group and at least the first semiconductive layer in the first layer group;
a means for controlling carrier concentration within the first and second semiconductor layers where first carrier concentrations being substantially constant across the first and second semiconductive layers within the ridge correspond to the ON state, second carrier concentrations being substantially depleted across the first and second semiconductive layers within the ridge correspond to the OFF state;
the carrier concentration controlling means including a conductive side gate that extends continuously across the first edges, the top of the ridge and the second edges;
a gate electrode disposed in conductive contact with the conductive side gate.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/464,512Filed 21 Mar 2017
Granted: 17 Oct 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

B82Y 10/00
Nanotechnology for information processing, storage or transmission
H10D 62/126
Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions: top-view geometrical layouts of…
H10D 30/506
Wherein the stacked channels have different properties: having different thicknesses, sizes or shapes
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]