Vertical single electron transistor formed by condensation

A method for forming a vertical single electron transistor, comprising;

• forming a nanowire from a first doped silicon layer, a SiGe layer, and a second doped silicon layer on a semiconductor substrate;
• depositing an oxide to cover the nanowire;
• performing a condensation process to convert the SiGe to oxide and condense Ge to form an island between the first doped silicon layer and the second doped silicon layer of the nanowire;
• and
• forming a source region about the first doped silicon layer.

A vertical single electron transistor, comprising;

• a nanowire having a lower doped layer and an upper doped layer;
• a dielectric gap disposed between the lower doped layer and the upper doped layer;
• a quantum dot formed within the dielectric gap and encapsulated in dielectric material;
• a source region formed about one of the lower doped layer and the upper doped layer;
• and
• a gate structure formed about the quantum dot.