Phase change memory with high endurance
AssigneesMacronix International Co., Ltd., International Business Machines Corporation
InventorsHsiang-Lan Lung, Wanki Kim, Matthew J. Brightsky, Chung Hon Lam
Life of this patent
Estimating the term…
Abstract
A plurality of memory cells in a cross-point array with improved endurance is disclosed. Each memory cell, disposed between first and second conductors, includes a switch in series with a pillar of phase change material. The pillar has a Te-rich material at one end proximal to the second conductor, and an Sb-rich material at the other end proximal to the first conductor, wherein the current direction is from the first conductor to the second conductor.
Claims19
An integrated circuit, comprising:
- a plurality of first conductors in a first patterned layer and a plurality of second conductors in a second patterned layer;
- and
- an array of memory cells disposed between the first conductors and the second conductors, each memory cell in the array comprising:
- a switch in series with a body of phase change material having an active region including first and second elements;
- a first buffer layer disposed in series between the active region and the switch, and including a higher concentration of the first element than the active region;
- and
- a second buffer layer disposed in series between the active region and the one of the first and second conductors disposed distal to the switch, and including a higher concentration of the second element than the active region.
A method of manufacturing an integrated circuit, comprising:
- forming a plurality of first conductors in a first patterned layer and a plurality of second conductors in a second patterned layer;
- and
- forming an array of memory cells disposed between the first conductors and the second conductors, each memory cell in the array comprising:
- a switch in series with a body of phase change material having an active region including first and second elements;
- a first buffer layer disposed in series between the active region and the switch, and including a higher concentration of the first element than the active region;
- and
- a second buffer layer disposed in series between the active region and the one of the first and second conductor disposed distal to the switch, and including a higher concentration of the second element than the active region.
An integrated circuit, comprising:
- a first conductor and a second conductor;
- and
- a memory cell disposed between the first and second conductors, the memory cell including an ovonic switch in series with a confined pillar including a body of phase change material comprising Sb and Te, the body having a first side proximal to the second conductor and a second side distal to the second conductor, the body having an active region, a first region in mass flow communication with the active region having a maximum concentration of Te on the first side proximal to the second conductor and a second region in mass flow communication with the active region having a maximum concentration of Sb on the second side distal to the second conductor, wherein a current direction is from the first conductor to the second conductor.
Dependencies are inferred from the claim text.