Resistive memory cell having a compact structure

A memory comprising:

• a semiconductor substrate;
• a first insulating layer covering the semiconductor substrate;
• a semiconductor active layer covering the insulating layer;
• a first trench formed through a lateral flank of the active layer and reaching the first insulating layer,
• a plurality of word lines formed on the semiconductor substrate;
• one or more source lines;
• and
• first and second memory cells, each of the first and second memory cells including:
• a selection transistor having a control gate, a first conduction terminal, and a second conduction terminal;
• and
• a variable-resistance element connected to the first conduction terminal, the variable-resistance element including a layer of variable-resistance material positioned in the first trench, and
• a trench conductor formed in the first trench and against a lateral flank of the layer of variable-resistance material, the control gates of the first and second memory cells being respectively connected to first and second word lines of the plurality of word lines, and the second conduction terminal of each selection transistor being connected to the one or more source lines, the variable-resistance elements of the first and second memory cells being formed in the first trench and separated from each other by the trench conductor, which is common to both of the first and second memory cells.

A memory comprising:

• a first memory cell that includes:
• a first selection transistor having a control gate and first and second conduction terminals, the first and second conduction terminals being positioned in a semiconductor layer;
• a first variable-resistance element connected to the first conduction terminal, the first variable-resistance element extending into the semiconductor layer;
• and
• a first insulating layer extending between a lateral sidewall of the control gate and the first variable-resistance element and between a portion of the top side of the control gate and a top side of the first variable-resistance element, the first insulating layer electrically insulating the control gate from the variable-resistance element;
• and
• a second memory cell that includes:
• a second selection transistor having a control gate and first and second conduction terminals, the first and second conduction terminals of the second selection transistor being positioned in the semiconductor layer;
• a second variable-resistance element connected to the first conduction terminal of the second selection transistor, the second variable-resistance element extending into the semiconductor layer and being separated from the first variable-resistance element by the trench conductor;
• and
• a second insulating layer extending between a lateral sidewall of the control gate of the second selection transistor and the second variable-resistance element and between a portion of the top side of the control gate of the second selection transistor and a top side of the second variable-resistance element, the second insulating layer electrically insulating the control gate of the second selection transistor from the second variable-resistance element.