Memory cell structures
AssigneesSemiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
InventorsHeng Cao, Shengfen Chiu
Life of this patent
Estimating the term…
Abstract
A memory cell includes a first diode, a second diode, and a random access memory cell element. The first diode and the random access memory cell element are series connected between a bit line and a word line. The second diode and the random access memory cell element are series connected between the word line and a reset line. A set path is formed through the first diode and the random access memory cell element, and a reset path is formed through the random access memory cell element and the second diode. The first diode is configured to performed a read operation and a set operation. The second diode is configured to perform a reset operation. The memory cell has higher forward current, lower leakage current and smaller size comparing with conventional memory cells.
Claims20
A memory cell, comprising:
- a first diode;
- a second diode;
- and
- a random access memory cell element,
- wherein:
- the first diode and the random access memory cell element are series connected between a bit line and a word line,
- the second diode and the random access memory cell element are series connected between the word line and a reset line,
- a set path is formed through the first diode and the random access memory cell element, and
- a reset path is formed through the random access memory cell element and the second diode.
A memory cell structure, comprising:
- a semiconductor substrate;
- a first diode in the semiconductor substrate;
- a second diode in the semiconductor substrate and on one side of the first diode, the first and second diodes each comprising a first electrode and a second electrode;
- a first isolation structure disposed in the semiconductor substrate between the first and second diodes;
- a bit line on the semiconductor substrate and extending along a first direction;
- a reset line on the semiconductor substrate and extending parallel to the bit line along the first direction;
- an interconnection metal layer on the semiconductor substrate between the bit line and the reset line and isolated from the bit line and the reset line;
- a first contact hole between the bit line and the first diode to electrically connect the first electrode of the first diode and the bit line;
- a second contact hole between the reset line and the second diode to electrically connect the reset line and the second electrode of the second diode;
- a third contact hole between the interconnection metal layer and the first diode to electrically connect the interconnection metal layer and the second electrode of the first diode;
- a fourth contact hole between the interconnection metal layer and the second diode to electrically connect the interconnection metal layer and the first electrode of the second diode;
- a random access memory element on the interconnection metal layer and having an end electrically connected to the interconnection metal layer;
- and
- a word line on the random access memory element and electrically connected to an opposite end of the random access memory element, the word line extending in a second direction substantially perpendicular to the first direction.
A memory cell array, comprising:
- M rows and N columns of memory cells, M and N being a natural number greater than one, wherein each memory cell comprises:
- a first diode;
- a second diode;
- and
- a random access memory cell element having a first end and a second end opposite the first end,
- wherein the first diode and the random access memory cell element are series connected between a bit line and a word line,
- wherein the second diode and the random access memory cell element are series connected in series between the word line and a reset line,
- wherein a set path is formed through the first diode and the random access memory cell element, and
- wherein a reset path is formed through the random access memory cell element and the second diode.
Dependencies are inferred from the claim text.