Embedded HKMG non-volatile memory

An integrated circuit (IC), comprising:

• a logic region comprising a logic device disposed over a substrate and including a first metal gate electrode disposed over a high-k gate dielectric layer;
• and
• an embedded memory region disposed adjacent to the logic region and comprising a non-volatile memory (NVM) device including a select transistor and a control transistor laterally spaced apart on the substrate;
• a sidewall spacer disposed along sidewalls of the first metal gate electrode, a control gate electrode of the control transistor, and a select gate electrode of the select transistor, wherein a contact etch stop layer is disposed between the logic region and the embedded memory region with a U shaped structure, wherein the U shaped structure abuts the sidewall spacer;
• wherein the select transistor or the control transistor comprises a second metal gate electrode separated from the substrate by the high-k gate dielectric layer and a memory gate oxide layer.

An integrated circuit (IC), comprising:

• a logic region comprising a logic device disposed over a substrate and including a first metal gate electrode disposed over a high-k gate dielectric layer and a logic gate oxide layer;
• and
• a memory region disposed adjacent to the logic region and comprising a non-volatile memory (NVM) device including a second metal gate electrode disposed over the high-k gate dielectric layer and a memory gate oxide layer;
• wherein the NVM device comprises a select transistor and a control transistor laterally spaced apart on the substrate, wherein the control transistor comprises a control gate electrode separated from the substrate by a charge trapping layer, the high-k gate dielectric layer and the memory gate oxide layer, and wherein the select transistor comprises a select gate electrode separated from the substrate by the high-k gate dielectric layer and the memory gate oxide layer;
• wherein the logic gate oxide layer comprises a second oxide layer disposed over a first oxide layer, and wherein the memory gate oxide layer comprises the second oxide layer disposed directly on the substrate.