Method of ONO stack formation
AssigneeCypress Semiconductor Corporation
InventorKrishnaswamy Ramkumar
Life of this patent
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Abstract
A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.
Claims19
A device, comprising:
- a non-volatile memory (NVM) transistor formed in a first region of a wafer, wherein the NVM transistor comprises an NV gate stack including a tunneling dielectric over a top surface of the wafer, a charge-trapping layer over the tunneling dielectric, and a blocking oxide over the charge-trapping layer, and wherein the blocking oxide includes a first thickness;
- a field-effect transistor (FET) formed in a second region of the wafer, wherein the FET comprises a gate oxide over the top surface of the wafer, and wherein the gate oxide is grown to a second thickness in a two-step oxidation process;
- and
- a nitride structure disposed over the NV gate stack, wherein the nitride structure changes energy levels of charge traps configured to be formed in the charge-trapping layer to increase charge retention of the charge trapping layer.
A device, comprising:
- a non-volatile memory (NVM) transistor formed in a first region of a wafer, wherein the NVM transistor comprises an NV gate stack including a tunneling dielectric over a top surface of the wafer, a charge-trapping layer over the tunneling dielectric, and a blocking oxide over the charge-trapping layer, wherein the blocking oxide includes a first thickness;
- a nitride structure disposed over the NV gate stack, wherein the nitride structure changes energy levels of charge traps configured to be formed in the charge-trapping layer to increase charge retention of the charge trapping layer;
- and
- a plurality of field-effect transistors (FETs) formed in a second region of the wafer, wherein each FET of the plurality of FETs comprises a gate oxide over the top surface of the wafer, and wherein the gate oxide of at least one FET of the plurality of FETs includes a second thickness,
- wherein a ratio between the first thickness and the second thickness is in an approximate range of 1:2.33 to 1:6.67.
A memory apparatus, comprising:
- a wafer divided into a plurality of first regions and second regions, wherein
- in each first region of the plurality of first regions, a non-volatile memory (NVM) transistor is formed, wherein the NVM transistor comprises an NV gate stack including a tunneling dielectric over a top surface of the wafer, a charge-trapping layer over the tunneling dielectric, and a blocking oxide over the charge-trapping layer, and wherein the blocking oxide includes a first thickness, wherein a nitride structure is disposed over the NV gate stack, wherein the nitride structure changes energy levels of charge traps configured to be formed in the charge-trapping layer to increase charge retention of the charge trapping layer, and
- in each second region of the plurality of second regions, at least one field-effect transistor (FET) is formed, wherein the at least one FET comprises a gate oxide over the top surface of the wafer, and wherein the gate oxide of the at least one FET is grown to a second thickness in a two-step oxidation process.
Dependencies are inferred from the claim text.