US 9,793,280 B2Granted

Integration of split gate flash memory array and logic devices

AssigneeSilicon Storage Technology, Inc.

InventorsChun-Ming Chen, Jeng-Wei Yang, Chien-Sheng Su, Man-Tang Wu, Nhan Do

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Abstract

A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

Claims18

Dependent claims

A memory device, comprising:

a semiconductor substrate having a memory area and a logic device area, wherein an upper surface of the substrate in the memory area is recessed lower than an upper surface of the substrate in the logic device area;
a plurality of memory cells formed in the memory area of the substrate, wherein each of the memory cells includes:
a first source region formed in the substrate,
a first drain region formed in the substrate, wherein a first channel region is defined in the substrate between the first source region and the first drain region,
a floating gate disposed over and insulated from a first portion of the first channel region that is adjacent to the first source region,
a control gate disposed over and insulated from the floating gate,
a select gate disposed over and insulated from a second portion of the first channel region that is adjacent to the first drain region, and
an erase gate disposed over and insulated from the first source region;
a plurality of logic devices formed in the logic device area of the substrate, wherein each of the logic devices includes:
a second source region formed in the substrate,
a second drain region formed in the substrate, wherein a second channel region is defined in the substrate between the second source region and the second drain region, and
a logic gate disposed over and insulated from the second channel region.

9 more elements

A method of forming a memory device, comprising:

forming one or more protective layers on a surface of a semiconductor substrate having a memory area and a logic device area;
removing the one or more protective layers from the memory device area of the substrate while preserving the one or more protective layers in the logic device area of the substrate;
performing an oxidation process that forms an oxide layer on the substrate surface in the memory area, wherein the oxidation process consumes and lowers a height of the substrate surface in the memory area such that the surface of the substrate in the memory area is recessed lower than the surface of the substrate in the logic device area;
removing the one or more protective layers from the logic device area of the substrate;
removing the oxide layer from the memory area of the substrate;
forming a plurality of memory cells in the memory area of the substrate, wherein each of the memory cells includes:
a first source region formed in the substrate,
a first drain region formed in the substrate, wherein a first channel region is defined in the substrate between the first source region and the first drain region,
a floating gate disposed over and insulated from a first portion of the first channel region that is adjacent to the first source region,
a control gate disposed over and insulated from the floating gate,
a select gate disposed over and insulated from a second portion of the first channel region that is adjacent to the first drain region, and
an erase gate disposed over and insulated from the first source region;
forming a plurality of logic devices in the logic device area of the substrate, wherein each of the logic devices includes:
a second source region formed in the substrate,
a second drain region formed in the substrate, wherein a second channel region is defined in the substrate between the second source region and the second drain region, and
a logic gate disposed over and insulated from the second channel region.

13 more elements

A method of forming a memory device, comprising:

forming one or more protective layers on a surface of a semiconductor substrate having a memory area and a logic device area;
removing the one or more protective layers from the logic device area of the substrate while preserving the one or more protective layers in the memory area of the substrate;
performing an epitaxial growth process that grows silicon on the substrate surface in the logic area, wherein the epitaxial growth process raises a height of the substrate surface in the logic device area such that the surface of the substrate in the logic device area is raised higher than the surface of the substrate in the memory area;
removing the one or more protective layers from the memory area of the substrate;
forming a plurality of memory cells in the memory area of the substrate, wherein each of the memory cells includes:
a first source region formed in the substrate,
a first drain region formed in the substrate, wherein a first channel region is defined in the substrate between the first source region and the first drain region,
a floating gate disposed over and insulated from a first portion of the first channel region that is adjacent to the first source region,
a control gate disposed over and insulated from the floating gate,
a select gate disposed over and insulated from a second portion of the first channel region that is adjacent to the first drain region, and
an erase gate disposed over and insulated from the first source region;
forming a plurality of logic devices in the logic device area of the substrate, wherein each of the logic devices includes:
a second source region formed in the substrate,
a second drain region formed in the substrate, wherein a second channel region is defined in the substrate between the second source region and the second drain region, and
a logic gate disposed over and insulated from the second channel region.

12 more elements

A method of forming a memory device, comprising:

forming one or more protective layers on a surface of a semiconductor substrate having a memory area and a logic device area;
removing the one or more protective layers from the logic device area of the substrate while preserving the one or more protective layers in the memory area of the substrate;
performing an epitaxial growth process that grows silicon on the substrate surface in the logic area, wherein the epitaxial growth process raises a height of the substrate surface in the logic device area such that the surface of the substrate in the logic device area is raised higher than the surface of the substrate in the memory area;
removing the one or more protective layers from the memory area of the substrate;
forming a plurality of memory cells in the memory area of the substrate, wherein each of the memory cells includes:
a first source region formed in the substrate,
a first drain region formed in the substrate, wherein a first channel region is defined in the substrate between the first source region and the first drain region,
a floating gate disposed over and insulated from a first portion of the first channel region that is adjacent the source region,
a control gate disposed over and insulated from the floating gate,
a select gate disposed over and insulated from a second portion of the first channel region that is adjacent to the drain region, and
an erase gate disposed over and insulated from the source region;
forming a plurality of logic devices in the logic device area of the substrate, wherein each of the logic devices includes:
a second source region formed in the substrate,
a second drain region formed in the substrate, wherein a second channel region is defined in the substrate between the second source region and the second drain region, and
a logic gate disposed over and insulated from the second channel region;
wherein:
the floating gates, the erase gates and the control gates are formed of polysilicon,
the select gates and the logic gates are formed of a metal material, and
the select gates are insulated from the substrate by at least a layer of oxide and a layer of high K material.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/057,590Filed 1 Mar 2016 · us provisional application
Priority: 4 Mar 2015
Published: US 2016/0260728 A18 Sep 2016
Granted: 17 Oct 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10B 41/42
Characterised by the peripheral circuit region: simultaneous manufacture of periphery and memory cells
H10B 41/43
Simultaneous manufacture of periphery and memory cells: comprising only one type of peripheral transistor
H10D 30/0411
Of FETs having insulated gates [IGFET]: of FETs having floating gates
H10D 30/6892
Characterised by the shapes, relative sizes or dispositions of the floating gate electrode: having at least one additional gate other than the…