Split gate non-volatile memory cell having a floating gate, word line, erase gate, and method of manufacturing

A memory device, comprising:

• a silicon semiconductor substrate;
• spaced apart source and drain regions formed in the silicon semiconductor substrate with a channel region there between;
• a conductive floating gate disposed over and insulated from a first portion of the channel region and a first portion of the source region;
• a conductive erase gate that includes:
• a first portion that is laterally adjacent to and insulated from the floating gate, and is over and insulated from the source region, and
• a second portion that extends up and over, and is insulated from, the floating gate;
• a conductive word line gate disposed over and insulated from a second portion of the channel region, wherein the word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate;
• wherein a thickness of insulation separating the word line gate from the second portion of the channel region is less than a thickness of insulation separating the floating gate from the erase gate, and wherein the erase gate second portion is the only conductive gate or conductive gate portion disposed over the floating gate.