Structure of memory cell with asymmetric cell structure and method for fabricating the same

A structure of memory cell, disposed on a substrate, a memory cell having a first gate structure of a first transistor and a second gate structure of a second transistor being adjacent to the first gate structure, the structure comprising:

• a first heavily doped region in the substrate adjacent to an outer side of the first gate structure, not between the first gate structure and the second gate structure;
• a first lightly doped drain (LDD) region with a first type dopant, disposed in the substrate between the first heavily doped region and the outer side of the first gate structure;
• a pocket doped region with a second type dopant, in the substrate overlapping with the first LDD region, wherein the second type dopant is opposite to the first type dopant in conductive type;
• a second heavily doped region in the substrate adjacent to an outer side of the second gate structure, opposite to the first heavily doped region, wherein the second heavily doped region is not between the first gate structure and the second gate structure, and no further heavily doped region is between the first gate structure and the second gate structure;
• and
• a second LDD region in the substrate with the first type dopant, disposed between the first gate structure and the second gate structure,
• wherein the first heavily doped region and the second heavily doped region are in same conductive type.