Semiconductor device with different fin pitches

A semiconductor device comprising:

• a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first distal end, a second distal end, and a medial region arranged between the first distal end and the second distal end, the first distal end of the first semiconductor fin arranged in a first source/drain region and the second distal end of the second semiconductor fin arranged in a second source/drain region;
• a second semiconductor fin arranged on the substrate, the second semiconductor fin having a first distal end, a second distal end, and a medial region arranged between the first distal end and the second distal end, the second distal end of the second semiconductor fin arranged in the first source/drain region and the second distal end of the second semiconductor fin arranged in the second source/drain region;
• a third semiconductor fin arranged on the substrate, the third semiconductor fin having a first distal end, a second distal end, and a medial region arranged between the first distal end and the second distal end, the first distal end and the second distal end of the third semiconductor fin arranged in the first source/drain region;
• wherein the first semiconductor fin, the second semiconductor fin, and the third semiconductor fin are arranged substantially in parallel with each other, the third semiconductor fin arranged between the first semiconductor fin and the second semiconductor fin, the first semiconductor fin arranged a first distance from the second semiconductor fin and the third semiconductor fin arranged a second distance from the first semiconductor fin, the first distance greater than the second distance;
• and
• a gate stack arranged over a channel region of the first semiconductor fin and the second semiconductor fin between the first source/drain region and the second source/drain region.

A semiconductor device, comprising:

• a first semiconductor fin structure in a first source/drain region on a substrate, the first semiconductor fin structure being defined by sides separated by a first distance;
• a second semiconductor fin structure in a channel region on the substrate, the second semiconductor fin structure being defined by sides separated by a second distance, the second distance being greater than the first distance, the first semiconductor fin structure contacting the second semiconductor fin structure;
• a third semiconductor fin structure in a second source/drain region on the substrate, the third semiconductor fin structure being defined by sides separated by a third distance, the second distance being greater than the third distance, the third semiconductor fin structure contacting the second semiconductor fin structure;
• and
• a gate stack arranged over the channel region of the second semiconductor fin structure.