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US 9,793,259 B2Granted
Integrated semiconductor device
AssigneeInfineon Technologies Americas Corp.
InventorMichael A. Briere
Life of this patent
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Abstract
A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.
Claims8
An integrated semiconductor device comprising:
- a silicon on insulator (SOI) substrate comprising a first silicon body, an insulation body formed on said first silicon body, and a second silicon body formed on said insulation body;
- a III-nitride heterostructure formed over a top surface of said SOI substrate, said heterostructure comprising a III-nitride buffer layer formed over said SOI substrate, a first III-nitride layer formed over said buffer layer, and a second III-nitride layer formed over said first III-nitride layer;
- a power transistor formed in said heterostructure;
- a driver circuit configured to drive said power transistor, said driver circuit comprising a silicon device formed in said second silicon body below said top surface;
- and
- a via extending through said heterostructure, through said second silicon body, and through said insulation body to make electrical contact between an electrode of said power transistor and said first silicon body, said via having walls lined by an insulation body and comprising conductive filler;
- wherein said power transistor includes a two-dimensional electron gas (2-DEG).
4 more elements
An integrated semiconductor device comprising:
- a silicon on insulator (SOI) substrate comprising a first silicon body, an insulation body formed on said first silicon body, and a second silicon body formed on said insulation body;
- a III-nitride heterostructure formed over a top surface of said SOI substrate, said heterostructure comprising a III-nitride buffer layer formed over said SOI substrate, a first III-nitride layer formed over said buffer layer, and a second III-nitride layer formed over said first III-nitride layer;
- a III-nitride power transistor formed in said heterostructure;
- a logic device formed in said second silicon body below said top surface, said logic device operatively coupled to a gate electrode of said III-nitride power transistor;
- a via extending through said heterostructure, through said second silicon body, and through said insulation body to make electrical contact between an electrode of said III-nitride power transistor and said first silicon body, said via having walls lined by an insulation body and comprising conductive filler;
- wherein said III-nitride power transistor includes a two-dimensional electron gas (2-DEG).
3 more elements
Dependencies are inferred from the claim text.