Chip package and manufacturing method thereof

A method of manufacturing a chip package, comprising:

• providing a first wafer, the first wafer including:
• a first substrate having a first surface and a second surface opposite to the first surface,
• a first passive element disposed on the first surface;
• a first protection layer covering the first passive element, the first protection layer has a third surface opposite to the first surface;
• and
• a first conductive pad structure and a second conductive pad structure disposed in the first protection layer and electrically connected to the first passive element;
• forming a first opening in the first protection layer to expose the first conductive pad structure;
• forming a second chip comprising:
• providing a second wafer, the second wafer including:
• a second substrate;
• an active element disposed underneath the second substrate;
• a second protection layer disposed underneath the second substrate and covering the active element;
• and
• a third conductive pad structure disposed in the second protection layer and electrically connected to the active element;
• forming a plurality of second through holes in the second protection layer to expose the third conductive pad structure;
• forming a second insulating layer underneath the second protection layer and extending to the second through hole to cover a wall of the second through hole;
• forming a second conductive layer underneath the second insulating layer and the third conductive pad structure, wherein the second conductive layer including:
• a second conductive portion disposed in and filled up the second through hole;
• and
• a plurality of second passive elements, wherein the second passive elements disposed in between the second through holes, and the second passive elements and the second conductive portion being connected;
• and
• forming a second barrier layer covering the second conductive layer;
• and
• forming a third opening in the second barrier layer to expose the second conductive portion;
• forming a first external conductive connection, wherein the second conductive portion directly electrically connected with the third conductive pad structure and the first external conductive connection;
• and
• connecting the second chip to the third surface of the first wafer such that the active element being electrically connected to the first conductive pad structure.