Semiconductor structure and method of forming
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Yu-Hsiang Hu, Hung-Jui Kuo
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Abstract
A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure.
Claims20
A method, comprising:
- providing a logic die and a memory die;
- forming a first conductive pillar over the logic die and a second conductive pillar over the memory die;
- forming a first passivation layer over the logic die;
- forming a molding compound extending along sidewalls of the logic die and the memory die;
- thinning the molding compound so that an upper surface of the molding compound is substantially planar with an upper surface of the first passivation layer, wherein a portion of the molding compound is disposed over the memory die after thinning;
- and
- forming a redistribution layer (RDL) structure over the molding compound, wherein the upper surface of the first passivation layer contacts a bottom surface of the RDL structure.
A method, comprising:
- receiving a first die, a first passivation layer and a first conductive pillar being disposed over the first die;
- receiving a second die, a second conductive pillar being disposed over the second die;
- forming a first redistribution layer (RDL) structure;
- placing the first die and the second die over the first RDL structure;
- forming a molding compound extending along sidewalls of the first die and the second die;
- thinning the molding compound to expose the first passivation layer, the first conductive pillar, the second conductive pillar, and a plurality of conductive vias;
- and
- forming a second RDL structure over the molding compound, wherein molding compound extends between a bottom surface of the second RDL structure and a top surface of the second die, and wherein the first passivation layer contacts the bottom surface of the second RDL structure.
A method, comprising:
- forming a first passivation layer on a logic die;
- depositing a second passivation layer on the first passivation layer on the logic die;
- curing the second passivation layer at a first temperature;
- disposing a first connector on the logic die, the first connector extending through the first passivation layer and the second passivation layer;
- forming a third passivation layer over a memory die;
- disposing a second connector on the memory die, the second connector extending through the third passivation layer;
- forming a molding material extending along sidewalls of the logic die and the memory die, wherein the molding material contacts a top surface of the second passivation layer;
- and
- forming a first redistribution layer over the molding material, the logic die, and the memory die, the first redistribution layer comprising one or more first conductive features disposed in a first dielectric layer, wherein the first connector and the second connector are electrically connected to a first conductive feature of the one or more first conductive features.
Dependencies are inferred from the claim text.