Detection of environmental conditions in a semiconductor chip
AssigneeIntel Deutschland GmbH
InventorsHans-Joachim Barth, Horst Baumeister, Peter Baumgartner, Philipp Riess, Jesenka Veledar Krueger
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Abstract
A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The capacitance may vary depending upon local environmental conditions such as mechanical stress (e.g., warpage or shear stress), mechanical pressure, temperature, and/or humidity. It may be desirable to provide a capacitor integrated into a semiconductor chip that is sufficiently small and sensitive to accurately measure conditions expected to be experienced by a semiconductor chip.
Claims21
A circuit, comprising:
- a first transistor having a gate, and further having a current path controlled by the gate of the first transistor and coupled between a first input node and a first node of a capacitor;
- a second transistor having a gate, and further having a current path controlled by the gate of the second transistor and coupled between a second input node and the first node of the capacitor;
- a third transistor having a gate, and further having a current path controlled by the gate of the third transistor and coupled between a third input node and a second node of the capacitor;
- a fourth transistor having a gate, and further having a current path controlled by the gate of the fourth transistor and coupled between a fourth input node and the second node of the capacitor;
- and
- a signal generator configured to generate a first periodic signal and a second periodic signal, and to supply the gates of the first and third transistors with the first periodic signal and the second and fourth transistors with the second periodic signal, wherein the first and second periodic signals are out of phase with each other by 180 degrees,
- wherein the first and second transistors are either all n-type transistors or all p-type transistors and the third and fourth transistors are either all n-type transistors or all p-type transistors.
A semiconductor chip comprising:
- a substrate;
- a plurality of layers of material disposed on the substrate;
- an active area of the semiconductor chip within which a plurality of circuit elements are disposed in at least some of the layers;
- and
- a capacitor disposed in a keep-out area of the semiconductor chip and electrically coupled to at least one of the circuit elements,
- wherein the circuit elements comprise a controller configured to determine a value based on a capacitance of the capacitor and wherein the controller is further configured to generate an early warning signal based on the determined value.
A semiconductor chip comprising:
- a substrate;
- a plurality of layers of material disposed on the substrate;
- a capacitor disposed in one or more of the layers and having a capacitance of less than 50 atto-Farads (aF);
- a circuit electrically coupled to the capacitor and configured to determine a value based on a capacitance of the capacitor to an accuracy of 5 aF or less, and to generate an early warning signal based on the determined value.
Dependencies are inferred from the claim text.