Plasma discharge path

A method of forming a device comprising:

• providing a semiconductor substrate;
• forming a second polarity type floating well in a device region in the substrate, the floating well is isolated from the substrate by a well isolation region surrounding the floating well;
• forming a first polarity type doped region in a discharge region of the substrate outside of the floating well, the first polarity type doped region serves as a first diode terminal;
• forming a second polarity type doped region in the floating well, the second polarity type doped region serves as a second diode terminal;
• completing front-end-of-line (FEOL) processing, including forming a first polarity type device in the device region;
• commencing back-end-of-line (BEOL) processing which includes forming a plurality of interlevel dielectric (ILD) levels on the substrate, wherein each of the ILD levels includes a via level with via contacts and a metal level with metal interconnects, and wherein the via level is disposed below the metal level;
• and
• forming a fuse unit having a fuse array in a fuse metal level which is one of the metal levels of the plurality of ILD levels, the fuse array having a plurality of fuses, the plurality of fuses of the fuse unit are horizontally aligned in the same fuse metal level, wherein the fuse unit comprises
• a first fuse terminal connected to the first diode terminal,
• a second fuse terminal connected to the second diode terminal,
• at least one fuse of the fuse array connecting the first and second fuse terminals, and
• wherein the fuse unit and diode form a discharger with a temporary discharge path from the floating well to the discharge region,
• the temporary discharge path is configured to discharge plasma charge from the floating well to the discharge region of the substrate during the BEOL processing,
• the temporary discharge path is configured to enable the first polarity type device to function after completion of the BEOL processing by blowing the plurality of fuses of the fuse unit with a fuse current, and
• the plurality of fuses of the fuse unit provides a large discharge path sufficient to dissipating all plasma charges from the floating well to the discharge region of the substrate while maintaining the fuse current below a damage threshold value which negatively impacts interconnect reliability.

A device comprising:

• a semiconductor substrate;
• a plurality of interlevel dielectric (ILD) layers disposed on the substrate, wherein each of the ILD levels comprises a metal level and a contact level;
• a device region in the substrate, the device region comprises a p-type floating well, the floating well is isolated from the substrate by a well isolation region surrounding the floating well;
• a n-type device disposed in the device region;
• a discharge region in the substrate comprising n-type dopants;
• and
• a discharger comprising a fuse unit, wherein the fuse unit is disposed in one of the metal levels of the ILD layers, the fuse unit comprises a fuse array having a plurality of fuses, wherein the plurality of fuses of the fuse unit are horizontally aligned in the same metal level, the discharger comprises a temporary discharge path from the device region to the discharge region, wherein
• the temporary discharge path is configured to discharge plasma charge from the floating well to the discharge region of the substrate during back-end-of-line (BEOL) processing,
• the temporary discharge path is configured to enable the n-type device to function after completion of the BEOL processing by blowing the plurality of fuses of the fuse unit with a fuse current, and
• the plurality of fuses of the fuse unit provides a large discharge path sufficient to dissipating all plasma charges from the floating well to the discharge region of the substrate while maintaining the fuse current below a damage threshold value which negatively impacts interconnect reliability.