System and method for measuring and improving overlay using electronic microscopic imaging and digital processing

A semiconductor fabrication system, comprising:

• a semiconductor fabrication tool configured to acquire an image of a portion of a wafer by scanning the portion of the wafer with a beam of electrons, the portion of the wafer including a metal line and a via hole disposed above the metal line, wherein the via hole exposes a portion of the metal line that is vertically aligned with the via hole, and wherein a first portion of the via hole and a second portion of the via hole are each vertically not aligned with the metal line and are disposed on opposite sides of the metal line;
• and
• one or more hardware processors configured to execute instructions to perform operations that include:
• processing the acquired image to enhance a contrast between the first portion and the second portion of the via hole and their surrounding areas;
• measuring a first dimension of the first portion of the via hole and measuring a second dimension of the second portion of the via hole, wherein the first dimension and the second dimension are each measured in a first direction that is different from a second direction along which the metal line extends;
• and
• determining an overlay between the via hole and the metal line based on the first dimension and the second dimension.

A method of semiconductor fabrication, comprising:

• acquiring an image of an edge portion of a wafer by scanning the edge portion of the wafer with a beam of electrons, the edge portion of the wafer including a metal line and a via hole disposed above the metal line, wherein the via hole exposes a portion of the metal line that is vertically aligned with the via hole, and wherein a first portion of the via hole and a second portion of the via hole are each vertically not aligned with the metal line and are disposed on opposite sides of the metal line;
• processing the acquired image to enhance a contrast between the first portion and the second portion of the via hole and their surrounding areas;
• measuring a first dimension of the first portion of the via hole and measuring a second dimension of the second portion of the via hole, wherein the first dimension and the second dimension are each measured in a first direction that is perpendicular to a second direction along which the metal line extends;
• determining an overlay between the via hole and the metal line at least in part by calculating a difference between the first dimension and the second dimension;
• and
• in response to determining that the overlay is greater than a predetermined limit, adjusting a subsequent lithography process performed to the wafer to reduce the overlay.