Method for producing interconnections for 3D integrated circuit
AssigneeCommissariat A L'energie Atomique Et Aux Energies Alternatives
InventorsClaire Fenouillet-Beranger, Philippe Coronel
Life of this patent
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Abstract
Method for producing one or more connection elements for integrated circuit including the formation of sacrificial elements passing through a porous layer formed between two superimposed levels of transistors, then the removal of the sacrificial elements through the porous layer and their replacement by a conductor material before or after having produced a higher level transistor.
Claims19
A method for producing one or more connection elements for an integrated circuit comprising:
- producing one or more sacrificial elements passing through at least one porous layer, the at least one porous layer surmounting a first transistor produced at least partially in a first semi-conductor layer, including forming one or more first openings passing through the at least one porous layer and filling the one or more first openings with a sacrificial material,
- forming a support on the at least one porous layer, the support including a second semi-conductor layer, wherein at least one second transistor is produced at least partially in the second semi-conductor layer,
- after producing the sacrificial elements, removing the one or more sacrificial elements using an etching agent of the sacrificial material introduced through the porous layer, and
- after forming the at least one second transistor, filling the one or more first openings by means of a conductor material so as to form connection elements using one or more second openings made in the support and emerging respectively on at least one of the first openings.
A method for producing one or more connection elements for an integrated circuit, comprising:
- producing one or more sacrificial elements passing through a first porous layer, the first porous layer formed on a first transistor produced at least partially in a first semi-conductor layer, including forming at least one first opening passing through the first porous layer and filling the at least one first opening with a sacrificial material,
- forming a second porous layer on the first porous layer and the one or more sacrificial elements such that the one or more sacrificial elements are completely surrounded by the first and second porous layers,
- removing the one or more sacrificial elements using an etching agent capable of being introduced through the first and second porous layers to produce at least one second opening,
- forming a second semi-conductor layer on the second porous layer, wherein at least one second transistor is formed at least partially in the second semi-conductor layer,
- forming at least one aperture through the second semi-conductor layer and the second porous layer to expose the at least one second opening, and
- filling the at least one second opening and the aperture with a conductor material so as to form connection elements.
Dependencies are inferred from the claim text.