Aggressive tip-to-tip scaling using subtractive integraton

A method for forming an interconnect structure comprising:

• forming a semiconductor structure on a semiconductor substrate, the semiconductor structure having a gate structure, shallow trench isolation and a source/drain;
• forming a dielectric over the gate structure;
• removing the dielectric adjacent to the gate structure to create a trench adjacent to the gate structure;
• depositing a metal into and filling the trench adjacent to the gate structure to form a metal line;
• lithographically defining an open area over the metal line;
• etching the metal line down to the shallow trench isolation or the source/drain through the open area to form a gap in the metal line so as to create segments of the metal line;
• and
• filling the gap down to the shallow trench isolation or the source/drain with a dielectric material to enable tip-to-tip spacing between the segments of the metal line.