Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects
AssigneeIntel Corporation
InventorsCharles H. Wallace, Paul A. Nyhus, Elliot N. Tan, Swaminathan Sivakumar
Life of this patent
Estimating the term…
Loading patent…
AssigneeIntel Corporation
InventorsCharles H. Wallace, Paul A. Nyhus, Elliot N. Tan, Swaminathan Sivakumar
Estimating the term…
Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line composed of alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.
A method of fabricating an interconnect structure for an integrated circuit, the method comprising:
A method of fabricating an interconnect structure for an integrated circuit, the method comprising:
Dependencies are inferred from the claim text.