Semiconductor manufacturing apparatus and semiconductor manufacturing method
AssigneeToshiba Memory Corporation
InventorsKazuyuki Miura, Kensuke Takahashi
Life of this patent
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Abstract
In one embodiment, a semiconductor manufacturing apparatus includes a stage provided in a chamber, and a conveying module configured to convey a plurality of wafers into the chamber and to set the plurality of wafers on the stage. The apparatus further includes a controller configured to divide treatment time for simultaneously treating the plurality of wafers on the stage into first to K-th treatment periods where K is an integer of two or more, and to change positions of one or more of the plurality of wafers on the stage by the conveying module according to the treatment periods.
Claims19
A semiconductor manufacturing apparatus comprising:
- a stage provided in a chamber;
- a conveying module configured to convey a plurality of wafers into the chamber and to set the plurality of wafers on the stage;
- a controller configured to divide treatment time for simultaneously treating the plurality of wafers on the stage into first to K-th treatment periods where K is an integer of two or more, and to change positions of one or more of the plurality of wafers on the stage by the conveying module according to the treatment periods.
A semiconductor manufacturing method comprising:
- conveying a plurality of wafers into a chamber;
- setting the plurality of wafers on a stage in the chamber;
- and
- dividing treatment time for simultaneously treating the plurality of wafers on the stage into first to K-th treatment periods where K is an integer of two or more, and changing positions of one or more of the plurality of wafers on the stage according to the treatment periods,
- wherein the division number K of the first to K-th treatment periods is equal to a number of the plurality of wafers.
A semiconductor manufacturing method comprising:
- conveying a plurality of wafers into a chamber;
- setting the plurality of wafers on a stage in the chamber;
- and
- dividing treatment time for simultaneously treating the plurality of wafers on the stage into first to K-th treatment periods where K is an integer of two or more, and changing positions of one or more of the plurality of wafers on the stage according to the treatment periods,
- wherein the division number K of the first to K-th treatment periods is less than a number of the plurality of wafers.
A semiconductor manufacturing method comprising:
- conveying a plurality of wafers into a chamber;
- setting the plurality of wafers on a stage in the chamber;
- and
- dividing treatment time for simultaneously treating the plurality of wafers on the stage into first to K-th treatment periods where K is an integer of two or more, and changing positions of one or more of the plurality of wafers on the stage according to the treatment periods,
- wherein:
- the plurality of wafers include first to N-th wafers where N is an integer of two or more, and
- the method further comprises accessing a process amount storage module configured to store first to N-th process amounts for the first to N-th wafers, and changing the positions of one or more of the first to N-th wafers so that process amounts of the first to N-th wafers in the first to K-th treatment periods respectively become the first to N-th process amounts.
A semiconductor manufacturing method comprising:
- conveying a plurality of wafers into a chamber;
- setting the plurality of wafers on a stage in the chamber;
- and
- dividing treatment time for simultaneously treating the plurality of wafers on the stage into first to K-th treatment periods where K is an integer of two or more, and changing positions of one or more of the plurality of wafers on the stage according to the treatment periods,
- wherein the treatment time is unequally divided into the first to K-th treatment periods.
Dependencies are inferred from the claim text.