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US 9,793,042 B2Granted
Printed circuit board having a layer structure
AssigneePhoenix Contact GmbH & Co. KG
InventorPeter Scholz
Life of this patent
Estimating the term…
Abstract
The invention relates to a printed circuit board having a layer structure, which accommodates a plurality of electric circuits. The electric circuits are separated from each other by an insulating barrier layer having a minimum thickness (Di) and a minimum distance (D0) between conductive components of the electric circuits.
Claims19
A printed circuit board having a layer structure with a galvanic isolation between individual electric circuits, comprising:
- a first coupling element associated with a first electric circuit;
- a first insulating spacer layer for spatially separating components of the first electric circuit;
- a second coupling element associated with a second electric circuit;
- a second insulating spacer layer for spatially separating components of the second electric circuit;
- and
- a first insulating barrier layer having a minimum thickness (Di) for achieving a high dielectric strength between the electric circuits;
- wherein adjacent to a third insulating spacer layer a second insulating barrier layer is provided which has, on a free side thereof, the second insulating spacer layer and components such as electrical/electronic components and conductive traces of a third electric circuit;
- wherein, in an overlapping and transfer region, the first and second coupling elements overlap each other with the first insulating barrier layer sandwiched therebetween to form a transformer;
- wherein with respect to the first coupling element or an associated ferrite plate, each transformer is surrounded by a first planar isolation region which extends along the surface of the printed circuit board to conductive components of the second circuit with a clearance and creepage distance of D0+X or D0+Y or D0+Z, and wherein with respect to the second coupling element or an associated ferrite plate, each transformer is surrounded by a second planar isolation region which extends along the surface of the printed circuit board to conductive components of the first circuit with a clearance and creepage distance of D0+X or D0+Y or D0+Z, wherein D0 is a minimum distance and X, Y, Z are additional lengths;
- and
- wherein electrical vias, if provided for power and signal supply of the first or second electric circuit and if embedded in the insulating barrier layer keep the minimum distance (D0) to conductive components of the respective adjacent electric circuit.
8 more elements
Dependencies are inferred from the claim text.