US 9,793,004 B2 · Shift register, gate driver, and display apparatus

Abstract

Disclosed is a shift register, a gate driver and a display apparatus. The shift register comprises: a pulling-up transistor (M3), a pulling-down transistor (M10), an output transistor (M12) and a reset unit, and further comprises an output pulling-down unit for discharging the output terminal and connected to a pulling-down node (PD) of a present stage, a pulling-down node (PD) of an adjacent stage, a low voltage signal terminal (VSS) and an output terminal (OUTPUT) respectively, which turns on the connection between the output terminal and the low voltage signal terminal (VSS) when the pulling-down node (PD) of the present stage or the pulling-down node (PD) of the adjacent stage is at a high level; and a controlling transistor (M14) having a gate connected to the pulling-up node (PU), a drain connected to the pulling-down node (PD) of the adjacent stage, and a source connected to the low voltage signal terminal (VSS). The shift register can effectively prevent the occurrence of the phenomenon of plural outputs by suppressing by the output pulling-down unit the noise in the output of each of the shift registers in the odd number of time unit and the even number of time unit after the operation of the shift register, thus increasing the stability of GOA unit and ensuring the display effect of the liquid crystal panel.

Claims17

Dependent claims

A shift register comprising:

a pulling-up transistor having a drain connected to a first clock signal terminal, a gate connected to a pulling-up node, and a source connected to an output terminal;
a first capacitor connected between the gate and the source of the pulling-up transistor;
a pulling-down transistor having a drain connected to the pulling-up node, a gate connected to a pulling-down node of a present stage, and a source connected to a low voltage signal terminal;
an output transistor having a gate connected to a second clock signal terminal, a drain connected to the output terminal, and a source connected to the low voltage signal terminal;
a reset unit connected to a reset signal terminal, the pulling-up node, the output terminal and the low voltage signal terminal respectively;
wherein the shift register further comprising:
an output pulling-down unit for discharging the output terminal and connected to the pulling-down node of the present stage, a pulling-down node of the adjacent stage, the low voltage signal terminal and the output terminal respectively.

4 more elements

A gate driver comprising a plurality of shift registers connected in cascade, the shift register comprises:

a pulling-up transistor having a drain connected to a first clock signal terminal, a gate connected to a pulling-up node, and a source connected to an output terminal;
a first capacitor connected between the gate and the source of the pulling-up transistor;
a pulling-down transistor having a drain connected to the pulling-up node, a gate connected to a pulling-down node of a present stage, and a source connected to a low voltage signal terminal;
an output transistor having a gate connected to a second clock signal terminal, a drain connected to the output terminal, and a source connected to the low voltage signal terminal;
a reset unit connected to a reset signal terminal, the pulling-up node, the output terminal and the low voltage signal terminal respectively;
wherein the shift register further comprising:
an output pulling-down unit for discharging the output terminal and connected to the pulling-down node of the present stage, a pulling-down node of the adjacent stage, the low voltage signal terminal and the output terminal respectively.

4 more elements

A display apparatus including a gate driver comprising a plurality of shift registers connected in cascade, the shift register comprises:

a pulling-up transistor having a drain connected to a first clock signal terminal, a gate connected to a pulling-up node, and a source connected to an output terminal;
a first capacitor connected between the gate and the source of the pulling-up transistor;
a pulling-down transistor having a drain connected to the pulling-up node, a gate connected to a pulling-down node of a present stage, and a source connected to a low voltage signal terminal;
an output transistor having a gate connected to a second clock signal terminal, a drain connected to the output terminal, and a source connected to the low voltage signal terminal;
a reset unit connected to a reset signal terminal, the pulling-up node, the output terminal and the low voltage signal terminal respectively;
wherein the shift register further comprising:
an output pulling-down unit for discharging the output terminal and connected to the pulling-down node of the present stage, a pulling-down node of the adjacent stage, the low voltage signal terminal and the output terminal respectively.

4 more elements

Dependencies are inferred from the claim text.

Shift register, gate driver, and display apparatus

Life of this patent

Shift register, gate driver, and display apparatus

Life of this patent

Abstract

Claims17